gccint: Standard Names
1
1 17.9 Standard Pattern Names For Generation
1 ==========================================
1
1 Here is a table of the instruction names that are meaningful in the RTL
1 generation pass of the compiler. Giving one of these names to an
1 instruction pattern tells the RTL generation pass that it can use the
1 pattern to accomplish a certain task.
1
1 'movM'
1 Here M stands for a two-letter machine mode name, in lowercase.
1 This instruction pattern moves data with that machine mode from
1 operand 1 to operand 0. For example, 'movsi' moves full-word data.
1
1 If operand 0 is a 'subreg' with mode M of a register whose own mode
1 is wider than M, the effect of this instruction is to store the
1 specified value in the part of the register that corresponds to
1 mode M. Bits outside of M, but which are within the same target
1 word as the 'subreg' are undefined. Bits which are outside the
1 target word are left unchanged.
1
1 This class of patterns is special in several ways. First of all,
1 each of these names up to and including full word size _must_ be
1 defined, because there is no other way to copy a datum from one
1 place to another. If there are patterns accepting operands in
1 larger modes, 'movM' must be defined for integer modes of those
1 sizes.
1
1 Second, these patterns are not used solely in the RTL generation
1 pass. Even the reload pass can generate move insns to copy values
1 from stack slots into temporary registers. When it does so, one of
1 the operands is a hard register and the other is an operand that
1 can need to be reloaded into a register.
1
1 Therefore, when given such a pair of operands, the pattern must
1 generate RTL which needs no reloading and needs no temporary
1 registers--no registers other than the operands. For example, if
1 you support the pattern with a 'define_expand', then in such a case
1 the 'define_expand' mustn't call 'force_reg' or any other such
1 function which might generate new pseudo registers.
1
1 This requirement exists even for subword modes on a RISC machine
1 where fetching those modes from memory normally requires several
1 insns and some temporary registers.
1
1 During reload a memory reference with an invalid address may be
1 passed as an operand. Such an address will be replaced with a
1 valid address later in the reload pass. In this case, nothing may
1 be done with the address except to use it as it stands. If it is
1 copied, it will not be replaced with a valid address. No attempt
1 should be made to make such an address into a valid address and no
1 routine (such as 'change_address') that will do so may be called.
1 Note that 'general_operand' will fail when applied to such an
1 address.
1
1 The global variable 'reload_in_progress' (which must be explicitly
1 declared if required) can be used to determine whether such special
1 handling is required.
1
1 The variety of operands that have reloads depends on the rest of
1 the machine description, but typically on a RISC machine these can
1 only be pseudo registers that did not get hard registers, while on
1 other machines explicit memory references will get optional
1 reloads.
1
1 If a scratch register is required to move an object to or from
1 memory, it can be allocated using 'gen_reg_rtx' prior to life
1 analysis.
1
1 If there are cases which need scratch registers during or after
1 reload, you must provide an appropriate secondary_reload target
1 hook.
1
1 The macro 'can_create_pseudo_p' can be used to determine if it is
1 unsafe to create new pseudo registers. If this variable is
1 nonzero, then it is unsafe to call 'gen_reg_rtx' to allocate a new
1 pseudo.
1
1 The constraints on a 'movM' must permit moving any hard register to
1 any other hard register provided that 'TARGET_HARD_REGNO_MODE_OK'
1 permits mode M in both registers and 'TARGET_REGISTER_MOVE_COST'
1 applied to their classes returns a value of 2.
1
1 It is obligatory to support floating point 'movM' instructions into
1 and out of any registers that can hold fixed point values, because
1 unions and structures (which have modes 'SImode' or 'DImode') can
1 be in those registers and they may have floating point members.
1
1 There may also be a need to support fixed point 'movM' instructions
1 in and out of floating point registers. Unfortunately, I have
1 forgotten why this was so, and I don't know whether it is still
1 true. If 'TARGET_HARD_REGNO_MODE_OK' rejects fixed point values in
1 floating point registers, then the constraints of the fixed point
1 'movM' instructions must be designed to avoid ever trying to reload
1 into a floating point register.
1
1 'reload_inM'
1 'reload_outM'
1 These named patterns have been obsoleted by the target hook
1 'secondary_reload'.
1
1 Like 'movM', but used when a scratch register is required to move
1 between operand 0 and operand 1. Operand 2 describes the scratch
1 register. See the discussion of the 'SECONDARY_RELOAD_CLASS' macro
1 in ⇒Register Classes.
1
1 There are special restrictions on the form of the 'match_operand's
1 used in these patterns. First, only the predicate for the reload
1 operand is examined, i.e., 'reload_in' examines operand 1, but not
1 the predicates for operand 0 or 2. Second, there may be only one
1 alternative in the constraints. Third, only a single register
1 class letter may be used for the constraint; subsequent constraint
1 letters are ignored. As a special exception, an empty constraint
1 string matches the 'ALL_REGS' register class. This may relieve
1 ports of the burden of defining an 'ALL_REGS' constraint letter
1 just for these patterns.
1
1 'movstrictM'
1 Like 'movM' except that if operand 0 is a 'subreg' with mode M of a
1 register whose natural mode is wider, the 'movstrictM' instruction
1 is guaranteed not to alter any of the register except the part
1 which belongs to mode M.
1
1 'movmisalignM'
1 This variant of a move pattern is designed to load or store a value
1 from a memory address that is not naturally aligned for its mode.
1 For a store, the memory will be in operand 0; for a load, the
1 memory will be in operand 1. The other operand is guaranteed not
1 to be a memory, so that it's easy to tell whether this is a load or
1 store.
1
1 This pattern is used by the autovectorizer, and when expanding a
1 'MISALIGNED_INDIRECT_REF' expression.
1
1 'load_multiple'
1 Load several consecutive memory locations into consecutive
1 registers. Operand 0 is the first of the consecutive registers,
1 operand 1 is the first memory location, and operand 2 is a
1 constant: the number of consecutive registers.
1
1 Define this only if the target machine really has such an
1 instruction; do not define this if the most efficient way of
1 loading consecutive registers from memory is to do them one at a
1 time.
1
1 On some machines, there are restrictions as to which consecutive
1 registers can be stored into memory, such as particular starting or
1 ending register numbers or only a range of valid counts. For those
1 machines, use a 'define_expand' (⇒Expander Definitions) and
1 make the pattern fail if the restrictions are not met.
1
1 Write the generated insn as a 'parallel' with elements being a
1 'set' of one register from the appropriate memory location (you may
1 also need 'use' or 'clobber' elements). Use a 'match_parallel'
1 (⇒RTL Template) to recognize the insn. See 'rs6000.md' for
1 examples of the use of this insn pattern.
1
1 'store_multiple'
1 Similar to 'load_multiple', but store several consecutive registers
1 into consecutive memory locations. Operand 0 is the first of the
1 consecutive memory locations, operand 1 is the first register, and
1 operand 2 is a constant: the number of consecutive registers.
1
1 'vec_load_lanesMN'
1 Perform an interleaved load of several vectors from memory operand
1 1 into register operand 0. Both operands have mode M. The
1 register operand is viewed as holding consecutive vectors of mode
1 N, while the memory operand is a flat array that contains the same
1 number of elements. The operation is equivalent to:
1
1 int c = GET_MODE_SIZE (M) / GET_MODE_SIZE (N);
1 for (j = 0; j < GET_MODE_NUNITS (N); j++)
1 for (i = 0; i < c; i++)
1 operand0[i][j] = operand1[j * c + i];
1
1 For example, 'vec_load_lanestiv4hi' loads 8 16-bit values from
1 memory into a register of mode 'TI'. The register contains two
1 consecutive vectors of mode 'V4HI'.
1
1 This pattern can only be used if:
1 TARGET_ARRAY_MODE_SUPPORTED_P (N, C)
1 is true. GCC assumes that, if a target supports this kind of
1 instruction for some mode N, it also supports unaligned loads for
1 vectors of mode N.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'vec_mask_load_lanesMN'
1 Like 'vec_load_lanesMN', but takes an additional mask operand
1 (operand 2) that specifies which elements of the destination
1 vectors should be loaded. Other elements of the destination
1 vectors are set to zero. The operation is equivalent to:
1
1 int c = GET_MODE_SIZE (M) / GET_MODE_SIZE (N);
1 for (j = 0; j < GET_MODE_NUNITS (N); j++)
1 if (operand2[j])
1 for (i = 0; i < c; i++)
1 operand0[i][j] = operand1[j * c + i];
1 else
1 for (i = 0; i < c; i++)
1 operand0[i][j] = 0;
1
1 This pattern is not allowed to 'FAIL'.
1
1 'vec_store_lanesMN'
1 Equivalent to 'vec_load_lanesMN', with the memory and register
1 operands reversed. That is, the instruction is equivalent to:
1
1 int c = GET_MODE_SIZE (M) / GET_MODE_SIZE (N);
1 for (j = 0; j < GET_MODE_NUNITS (N); j++)
1 for (i = 0; i < c; i++)
1 operand0[j * c + i] = operand1[i][j];
1
1 for a memory operand 0 and register operand 1.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'vec_mask_store_lanesMN'
1 Like 'vec_store_lanesMN', but takes an additional mask operand
1 (operand 2) that specifies which elements of the source vectors
1 should be stored. The operation is equivalent to:
1
1 int c = GET_MODE_SIZE (M) / GET_MODE_SIZE (N);
1 for (j = 0; j < GET_MODE_NUNITS (N); j++)
1 if (operand2[j])
1 for (i = 0; i < c; i++)
1 operand0[j * c + i] = operand1[i][j];
1
1 This pattern is not allowed to 'FAIL'.
1
1 'gather_loadM'
1 Load several separate memory locations into a vector of mode M.
1 Operand 1 is a scalar base address and operand 2 is a vector of
1 offsets from that base. Operand 0 is a destination vector with the
1 same number of elements as the offset. For each element index I:
1
1 * extend the offset element I to address width, using zero
1 extension if operand 3 is 1 and sign extension if operand 3 is
1 zero;
1 * multiply the extended offset by operand 4;
1 * add the result to the base; and
1 * load the value at that address into element I of operand 0.
1
1 The value of operand 3 does not matter if the offsets are already
1 address width.
1
1 'mask_gather_loadM'
1 Like 'gather_loadM', but takes an extra mask operand as operand 5.
1 Bit I of the mask is set if element I of the result should be
1 loaded from memory and clear if element I of the result should be
1 set to zero.
1
1 'scatter_storeM'
1 Store a vector of mode M into several distinct memory locations.
1 Operand 0 is a scalar base address and operand 1 is a vector of
1 offsets from that base. Operand 4 is the vector of values that
1 should be stored, which has the same number of elements as the
1 offset. For each element index I:
1
1 * extend the offset element I to address width, using zero
1 extension if operand 2 is 1 and sign extension if operand 2 is
1 zero;
1 * multiply the extended offset by operand 3;
1 * add the result to the base; and
1 * store element I of operand 4 to that address.
1
1 The value of operand 2 does not matter if the offsets are already
1 address width.
1
1 'mask_scatter_storeM'
1 Like 'scatter_storeM', but takes an extra mask operand as operand
1 5. Bit I of the mask is set if element I of the result should be
1 stored to memory.
1
1 'vec_setM'
1 Set given field in the vector value. Operand 0 is the vector to
1 modify, operand 1 is new value of field and operand 2 specify the
1 field index.
1
1 'vec_extractMN'
1 Extract given field from the vector value. Operand 1 is the
1 vector, operand 2 specify field index and operand 0 place to store
1 value into. The N mode is the mode of the field or vector of
1 fields that should be extracted, should be either element mode of
1 the vector mode M, or a vector mode with the same element mode and
1 smaller number of elements. If N is a vector mode, the index is
1 counted in units of that mode.
1
1 'vec_initMN'
1 Initialize the vector to given values. Operand 0 is the vector to
1 initialize and operand 1 is parallel containing values for
1 individual fields. The N mode is the mode of the elements, should
1 be either element mode of the vector mode M, or a vector mode with
1 the same element mode and smaller number of elements.
1
1 'vec_duplicateM'
1 Initialize vector output operand 0 so that each element has the
1 value given by scalar input operand 1. The vector has mode M and
1 the scalar has the mode appropriate for one element of M.
1
1 This pattern only handles duplicates of non-constant inputs.
1 Constant vectors go through the 'movM' pattern instead.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'vec_seriesM'
1 Initialize vector output operand 0 so that element I is equal to
1 operand 1 plus I times operand 2. In other words, create a linear
1 series whose base value is operand 1 and whose step is operand 2.
1
1 The vector output has mode M and the scalar inputs have the mode
1 appropriate for one element of M. This pattern is not used for
1 floating-point vectors, in order to avoid having to specify the
1 rounding behavior for I > 1.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'while_ultMN'
1 Set operand 0 to a mask that is true while incrementing operand 1
1 gives a value that is less than operand 2. Operand 0 has mode N
1 and operands 1 and 2 are scalar integers of mode M. The operation
1 is equivalent to:
1
1 operand0[0] = operand1 < operand2;
1 for (i = 1; i < GET_MODE_NUNITS (N); i++)
1 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
1
1 'vec_cmpMN'
1 Output a vector comparison. Operand 0 of mode N is the destination
1 for predicate in operand 1 which is a signed vector comparison with
1 operands of mode M in operands 2 and 3. Predicate is computed by
1 element-wise evaluation of the vector comparison with a truth value
1 of all-ones and a false value of all-zeros.
1
1 'vec_cmpuMN'
1 Similar to 'vec_cmpMN' but perform unsigned vector comparison.
1
1 'vec_cmpeqMN'
1 Similar to 'vec_cmpMN' but perform equality or non-equality vector
1 comparison only. If 'vec_cmpMN' or 'vec_cmpuMN' instruction
1 pattern is supported, it will be preferred over 'vec_cmpeqMN', so
1 there is no need to define this instruction pattern if the others
1 are supported.
1
1 'vcondMN'
1 Output a conditional vector move. Operand 0 is the destination to
1 receive a combination of operand 1 and operand 2, which are of mode
1 M, dependent on the outcome of the predicate in operand 3 which is
1 a signed vector comparison with operands of mode N in operands 4
1 and 5. The modes M and N should have the same size. Operand 0
1 will be set to the value OP1 & MSK | OP2 & ~MSK where MSK is
1 computed by element-wise evaluation of the vector comparison with a
1 truth value of all-ones and a false value of all-zeros.
1
1 'vconduMN'
1 Similar to 'vcondMN' but performs unsigned vector comparison.
1
1 'vcondeqMN'
1 Similar to 'vcondMN' but performs equality or non-equality vector
1 comparison only. If 'vcondMN' or 'vconduMN' instruction pattern is
1 supported, it will be preferred over 'vcondeqMN', so there is no
1 need to define this instruction pattern if the others are
1 supported.
1
1 'vcond_mask_MN'
1 Similar to 'vcondMN' but operand 3 holds a pre-computed result of
1 vector comparison.
1
1 'maskloadMN'
1 Perform a masked load of vector from memory operand 1 of mode M
1 into register operand 0. Mask is provided in register operand 2 of
1 mode N.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'maskstoreMN'
1 Perform a masked store of vector from register operand 1 of mode M
1 into memory operand 0. Mask is provided in register operand 2 of
1 mode N.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'vec_permM'
1 Output a (variable) vector permutation. Operand 0 is the
1 destination to receive elements from operand 1 and operand 2, which
1 are of mode M. Operand 3 is the "selector". It is an integral
1 mode vector of the same width and number of elements as mode M.
1
1 The input elements are numbered from 0 in operand 1 through 2*N-1
1 in operand 2. The elements of the selector must be computed modulo
1 2*N. Note that if 'rtx_equal_p(operand1, operand2)', this can be
1 implemented with just operand 1 and selector elements modulo N.
1
1 In order to make things easy for a number of targets, if there is
1 no 'vec_perm' pattern for mode M, but there is for mode Q where Q
1 is a vector of 'QImode' of the same width as M, the middle-end will
1 lower the mode M 'VEC_PERM_EXPR' to mode Q.
1
1 See also 'TARGET_VECTORIZER_VEC_PERM_CONST', which performs the
1 analogous operation for constant selectors.
1
1 'pushM1'
1 Output a push instruction. Operand 0 is value to push. Used only
1 when 'PUSH_ROUNDING' is defined. For historical reason, this
1 pattern may be missing and in such case an 'mov' expander is used
1 instead, with a 'MEM' expression forming the push operation. The
1 'mov' expander method is deprecated.
1
1 'addM3'
1 Add operand 2 and operand 1, storing the result in operand 0. All
1 operands must have mode M. This can be used even on two-address
1 machines, by means of constraints requiring operands 1 and 0 to be
1 the same location.
1
1 'ssaddM3', 'usaddM3'
1 'subM3', 'sssubM3', 'ussubM3'
1 'mulM3', 'ssmulM3', 'usmulM3'
1 'divM3', 'ssdivM3'
1 'udivM3', 'usdivM3'
1 'modM3', 'umodM3'
1 'uminM3', 'umaxM3'
1 'andM3', 'iorM3', 'xorM3'
1 Similar, for other arithmetic operations.
1
1 'addvM4'
1 Like 'addM3' but takes a 'code_label' as operand 3 and emits code
1 to jump to it if signed overflow occurs during the addition. This
1 pattern is used to implement the built-in functions performing
1 signed integer addition with overflow checking.
1
1 'subvM4', 'mulvM4'
1 Similar, for other signed arithmetic operations.
1
1 'uaddvM4'
1 Like 'addvM4' but for unsigned addition. That is to say, the
1 operation is the same as signed addition but the jump is taken only
1 on unsigned overflow.
1
1 'usubvM4', 'umulvM4'
1 Similar, for other unsigned arithmetic operations.
1
1 'addptrM3'
1 Like 'addM3' but is guaranteed to only be used for address
1 calculations. The expanded code is not allowed to clobber the
1 condition code. It only needs to be defined if 'addM3' sets the
1 condition code. If adds used for address calculations and normal
1 adds are not compatible it is required to expand a distinct pattern
1 (e.g. using an unspec). The pattern is used by LRA to emit
1 address calculations. 'addM3' is used if 'addptrM3' is not
1 defined.
1
1 'fmaM4'
1 Multiply operand 2 and operand 1, then add operand 3, storing the
1 result in operand 0 without doing an intermediate rounding step.
1 All operands must have mode M. This pattern is used to implement
1 the 'fma', 'fmaf', and 'fmal' builtin functions from the ISO C99
1 standard.
1
1 'fmsM4'
1 Like 'fmaM4', except operand 3 subtracted from the product instead
1 of added to the product. This is represented in the rtl as
1
1 (fma:M OP1 OP2 (neg:M OP3))
1
1 'fnmaM4'
1 Like 'fmaM4' except that the intermediate product is negated before
1 being added to operand 3. This is represented in the rtl as
1
1 (fma:M (neg:M OP1) OP2 OP3)
1
1 'fnmsM4'
1 Like 'fmsM4' except that the intermediate product is negated before
1 subtracting operand 3. This is represented in the rtl as
1
1 (fma:M (neg:M OP1) OP2 (neg:M OP3))
1
1 'sminM3', 'smaxM3'
1 Signed minimum and maximum operations. When used with floating
1 point, if both operands are zeros, or if either operand is 'NaN',
1 then it is unspecified which of the two operands is returned as the
1 result.
1
1 'fminM3', 'fmaxM3'
1 IEEE-conformant minimum and maximum operations. If one operand is
1 a quiet 'NaN', then the other operand is returned. If both
1 operands are quiet 'NaN', then a quiet 'NaN' is returned. In the
1 case when gcc supports signaling 'NaN' (-fsignaling-nans) an
1 invalid floating point exception is raised and a quiet 'NaN' is
1 returned.
1
1 All operands have mode M, which is a scalar or vector
1 floating-point mode. These patterns are not allowed to 'FAIL'.
1
1 'reduc_smin_scal_M', 'reduc_smax_scal_M'
1 Find the signed minimum/maximum of the elements of a vector. The
1 vector is operand 1, and operand 0 is the scalar result, with mode
1 equal to the mode of the elements of the input vector.
1
1 'reduc_umin_scal_M', 'reduc_umax_scal_M'
1 Find the unsigned minimum/maximum of the elements of a vector. The
1 vector is operand 1, and operand 0 is the scalar result, with mode
1 equal to the mode of the elements of the input vector.
1
1 'reduc_plus_scal_M'
1 Compute the sum of the elements of a vector. The vector is operand
1 1, and operand 0 is the scalar result, with mode equal to the mode
1 of the elements of the input vector.
1
1 'reduc_and_scal_M'
1 'reduc_ior_scal_M'
1 'reduc_xor_scal_M'
1 Compute the bitwise 'AND'/'IOR'/'XOR' reduction of the elements of
1 a vector of mode M. Operand 1 is the vector input and operand 0 is
1 the scalar result. The mode of the scalar result is the same as
1 one element of M.
1
1 'extract_last_M'
1 Find the last set bit in mask operand 1 and extract the associated
1 element of vector operand 2. Store the result in scalar operand 0.
1 Operand 2 has vector mode M while operand 0 has the mode
1 appropriate for one element of M. Operand 1 has the usual mask
1 mode for vectors of mode M; see 'TARGET_VECTORIZE_GET_MASK_MODE'.
1
1 'fold_extract_last_M'
1 If any bits of mask operand 2 are set, find the last set bit,
1 extract the associated element from vector operand 3, and store the
1 result in operand 0. Store operand 1 in operand 0 otherwise.
1 Operand 3 has mode M and operands 0 and 1 have the mode appropriate
1 for one element of M. Operand 2 has the usual mask mode for
1 vectors of mode M; see 'TARGET_VECTORIZE_GET_MASK_MODE'.
1
1 'fold_left_plus_M'
1 Take scalar operand 1 and successively add each element from vector
1 operand 2. Store the result in scalar operand 0. The vector has
1 mode M and the scalars have the mode appropriate for one element of
1 M. The operation is strictly in-order: there is no reassociation.
1
1 'sdot_prodM'
1 'udot_prodM'
1 Compute the sum of the products of two signed/unsigned elements.
1 Operand 1 and operand 2 are of the same mode. Their product, which
1 is of a wider mode, is computed and added to operand 3. Operand 3
1 is of a mode equal or wider than the mode of the product. The
1 result is placed in operand 0, which is of the same mode as operand
1 3.
1
1 'ssadM'
1 'usadM'
1 Compute the sum of absolute differences of two signed/unsigned
1 elements. Operand 1 and operand 2 are of the same mode. Their
1 absolute difference, which is of a wider mode, is computed and
1 added to operand 3. Operand 3 is of a mode equal or wider than the
1 mode of the absolute difference. The result is placed in operand
1 0, which is of the same mode as operand 3.
1
1 'widen_ssumM3'
1 'widen_usumM3'
1 Operands 0 and 2 are of the same mode, which is wider than the mode
1 of operand 1. Add operand 1 to operand 2 and place the widened
1 result in operand 0. (This is used express accumulation of
1 elements into an accumulator of a wider mode.)
1
1 'vec_shl_insert_M'
1 Shift the elements in vector input operand 1 left one element (i.e.
1 away from element 0) and fill the vacated element 0 with the scalar
1 in operand 2. Store the result in vector output operand 0.
1 Operands 0 and 1 have mode M and operand 2 has the mode appropriate
1 for one element of M.
1
1 'vec_shr_M'
1 Whole vector right shift in bits, i.e. towards element 0. Operand
1 1 is a vector to be shifted. Operand 2 is an integer shift amount
1 in bits. Operand 0 is where the resulting shifted vector is
1 stored. The output and input vectors should have the same modes.
1
1 'vec_pack_trunc_M'
1 Narrow (demote) and merge the elements of two vectors. Operands 1
1 and 2 are vectors of the same mode having N integral or floating
1 point elements of size S. Operand 0 is the resulting vector in
1 which 2*N elements of size N/2 are concatenated after narrowing
1 them down using truncation.
1
1 'vec_pack_ssat_M', 'vec_pack_usat_M'
1 Narrow (demote) and merge the elements of two vectors. Operands 1
1 and 2 are vectors of the same mode having N integral elements of
1 size S. Operand 0 is the resulting vector in which the elements of
1 the two input vectors are concatenated after narrowing them down
1 using signed/unsigned saturating arithmetic.
1
1 'vec_pack_sfix_trunc_M', 'vec_pack_ufix_trunc_M'
1 Narrow, convert to signed/unsigned integral type and merge the
1 elements of two vectors. Operands 1 and 2 are vectors of the same
1 mode having N floating point elements of size S. Operand 0 is the
1 resulting vector in which 2*N elements of size N/2 are
1 concatenated.
1
1 'vec_unpacks_hi_M', 'vec_unpacks_lo_M'
1 Extract and widen (promote) the high/low part of a vector of signed
1 integral or floating point elements. The input vector (operand 1)
1 has N elements of size S. Widen (promote) the high/low elements of
1 the vector using signed or floating point extension and place the
1 resulting N/2 values of size 2*S in the output vector (operand 0).
1
1 'vec_unpacku_hi_M', 'vec_unpacku_lo_M'
1 Extract and widen (promote) the high/low part of a vector of
1 unsigned integral elements. The input vector (operand 1) has N
1 elements of size S. Widen (promote) the high/low elements of the
1 vector using zero extension and place the resulting N/2 values of
1 size 2*S in the output vector (operand 0).
1
1 'vec_unpacks_float_hi_M', 'vec_unpacks_float_lo_M'
1 'vec_unpacku_float_hi_M', 'vec_unpacku_float_lo_M'
1 Extract, convert to floating point type and widen the high/low part
1 of a vector of signed/unsigned integral elements. The input vector
1 (operand 1) has N elements of size S. Convert the high/low
1 elements of the vector using floating point conversion and place
1 the resulting N/2 values of size 2*S in the output vector (operand
1 0).
1
1 'vec_widen_umult_hi_M', 'vec_widen_umult_lo_M'
1 'vec_widen_smult_hi_M', 'vec_widen_smult_lo_M'
1 'vec_widen_umult_even_M', 'vec_widen_umult_odd_M'
1 'vec_widen_smult_even_M', 'vec_widen_smult_odd_M'
1 Signed/Unsigned widening multiplication. The two inputs (operands
1 1 and 2) are vectors with N signed/unsigned elements of size S.
1 Multiply the high/low or even/odd elements of the two vectors, and
1 put the N/2 products of size 2*S in the output vector (operand 0).
1 A target shouldn't implement even/odd pattern pair if it is less
1 efficient than lo/hi one.
1
1 'vec_widen_ushiftl_hi_M', 'vec_widen_ushiftl_lo_M'
1 'vec_widen_sshiftl_hi_M', 'vec_widen_sshiftl_lo_M'
1 Signed/Unsigned widening shift left. The first input (operand 1)
1 is a vector with N signed/unsigned elements of size S. Operand 2
1 is a constant. Shift the high/low elements of operand 1, and put
1 the N/2 results of size 2*S in the output vector (operand 0).
1
1 'mulhisi3'
1 Multiply operands 1 and 2, which have mode 'HImode', and store a
1 'SImode' product in operand 0.
1
1 'mulqihi3', 'mulsidi3'
1 Similar widening-multiplication instructions of other widths.
1
1 'umulqihi3', 'umulhisi3', 'umulsidi3'
1 Similar widening-multiplication instructions that do unsigned
1 multiplication.
1
1 'usmulqihi3', 'usmulhisi3', 'usmulsidi3'
1 Similar widening-multiplication instructions that interpret the
1 first operand as unsigned and the second operand as signed, then do
1 a signed multiplication.
1
1 'smulM3_highpart'
1 Perform a signed multiplication of operands 1 and 2, which have
1 mode M, and store the most significant half of the product in
1 operand 0. The least significant half of the product is discarded.
1
1 'umulM3_highpart'
1 Similar, but the multiplication is unsigned.
1
1 'maddMN4'
1 Multiply operands 1 and 2, sign-extend them to mode N, add operand
1 3, and store the result in operand 0. Operands 1 and 2 have mode M
1 and operands 0 and 3 have mode N. Both modes must be integer or
1 fixed-point modes and N must be twice the size of M.
1
1 In other words, 'maddMN4' is like 'mulMN3' except that it also adds
1 operand 3.
1
1 These instructions are not allowed to 'FAIL'.
1
1 'umaddMN4'
1 Like 'maddMN4', but zero-extend the multiplication operands instead
1 of sign-extending them.
1
1 'ssmaddMN4'
1 Like 'maddMN4', but all involved operations must be
1 signed-saturating.
1
1 'usmaddMN4'
1 Like 'umaddMN4', but all involved operations must be
1 unsigned-saturating.
1
1 'msubMN4'
1 Multiply operands 1 and 2, sign-extend them to mode N, subtract the
1 result from operand 3, and store the result in operand 0. Operands
1 1 and 2 have mode M and operands 0 and 3 have mode N. Both modes
1 must be integer or fixed-point modes and N must be twice the size
1 of M.
1
1 In other words, 'msubMN4' is like 'mulMN3' except that it also
1 subtracts the result from operand 3.
1
1 These instructions are not allowed to 'FAIL'.
1
1 'umsubMN4'
1 Like 'msubMN4', but zero-extend the multiplication operands instead
1 of sign-extending them.
1
1 'ssmsubMN4'
1 Like 'msubMN4', but all involved operations must be
1 signed-saturating.
1
1 'usmsubMN4'
1 Like 'umsubMN4', but all involved operations must be
1 unsigned-saturating.
1
1 'divmodM4'
1 Signed division that produces both a quotient and a remainder.
1 Operand 1 is divided by operand 2 to produce a quotient stored in
1 operand 0 and a remainder stored in operand 3.
1
1 For machines with an instruction that produces both a quotient and
1 a remainder, provide a pattern for 'divmodM4' but do not provide
1 patterns for 'divM3' and 'modM3'. This allows optimization in the
1 relatively common case when both the quotient and remainder are
1 computed.
1
1 If an instruction that just produces a quotient or just a remainder
1 exists and is more efficient than the instruction that produces
1 both, write the output routine of 'divmodM4' to call
1 'find_reg_note' and look for a 'REG_UNUSED' note on the quotient or
1 remainder and generate the appropriate instruction.
1
1 'udivmodM4'
1 Similar, but does unsigned division.
1
1 'ashlM3', 'ssashlM3', 'usashlM3'
1 Arithmetic-shift operand 1 left by a number of bits specified by
1 operand 2, and store the result in operand 0. Here M is the mode
1 of operand 0 and operand 1; operand 2's mode is specified by the
1 instruction pattern, and the compiler will convert the operand to
1 that mode before generating the instruction. The shift or rotate
1 expander or instruction pattern should explicitly specify the mode
1 of the operand 2, it should never be 'VOIDmode'. The meaning of
1 out-of-range shift counts can optionally be specified by
11 'TARGET_SHIFT_TRUNCATION_MASK'. ⇒
TARGET_SHIFT_TRUNCATION_MASK. Operand 2 is always a scalar type.
1
1 'ashrM3', 'lshrM3', 'rotlM3', 'rotrM3'
1 Other shift and rotate instructions, analogous to the 'ashlM3'
1 instructions. Operand 2 is always a scalar type.
1
1 'vashlM3', 'vashrM3', 'vlshrM3', 'vrotlM3', 'vrotrM3'
1 Vector shift and rotate instructions that take vectors as operand 2
1 instead of a scalar type.
1
1 'bswapM2'
1 Reverse the order of bytes of operand 1 and store the result in
1 operand 0.
1
1 'negM2', 'ssnegM2', 'usnegM2'
1 Negate operand 1 and store the result in operand 0.
1
1 'negvM3'
1 Like 'negM2' but takes a 'code_label' as operand 2 and emits code
1 to jump to it if signed overflow occurs during the negation.
1
1 'absM2'
1 Store the absolute value of operand 1 into operand 0.
1
1 'sqrtM2'
1 Store the square root of operand 1 into operand 0. Both operands
1 have mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'rsqrtM2'
1 Store the reciprocal of the square root of operand 1 into operand
1 0. Both operands have mode M, which is a scalar or vector
1 floating-point mode.
1
1 On most architectures this pattern is only approximate, so either
1 its C condition or the 'TARGET_OPTAB_SUPPORTED_P' hook should check
1 for the appropriate math flags. (Using the C condition is more
1 direct, but using 'TARGET_OPTAB_SUPPORTED_P' can be useful if a
1 target-specific built-in also uses the 'rsqrtM2' pattern.)
1
1 This pattern is not allowed to 'FAIL'.
1
1 'fmodM3'
1 Store the remainder of dividing operand 1 by operand 2 into operand
1 0, rounded towards zero to an integer. All operands have mode M,
1 which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'remainderM3'
1 Store the remainder of dividing operand 1 by operand 2 into operand
1 0, rounded to the nearest integer. All operands have mode M, which
1 is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'scalbM3'
1 Raise 'FLT_RADIX' to the power of operand 2, multiply it by operand
1 1, and store the result in operand 0. All operands have mode M,
1 which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'ldexpM3'
1 Raise 2 to the power of operand 2, multiply it by operand 1, and
1 store the result in operand 0. Operands 0 and 1 have mode M, which
1 is a scalar or vector floating-point mode. Operand 2's mode has
1 the same number of elements as M and each element is wide enough to
1 store an 'int'. The integers are signed.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'cosM2'
1 Store the cosine of operand 1 into operand 0. Both operands have
1 mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'sinM2'
1 Store the sine of operand 1 into operand 0. Both operands have
1 mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'sincosM3'
1 Store the cosine of operand 2 into operand 0 and the sine of
1 operand 2 into operand 1. All operands have mode M, which is a
1 scalar or vector floating-point mode.
1
1 Targets that can calculate the sine and cosine simultaneously can
1 implement this pattern as opposed to implementing individual
1 'sinM2' and 'cosM2' patterns. The 'sin' and 'cos' built-in
1 functions will then be expanded to the 'sincosM3' pattern, with one
1 of the output values left unused.
1
1 'tanM2'
1 Store the tangent of operand 1 into operand 0. Both operands have
1 mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'asinM2'
1 Store the arc sine of operand 1 into operand 0. Both operands have
1 mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'acosM2'
1 Store the arc cosine of operand 1 into operand 0. Both operands
1 have mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'atanM2'
1 Store the arc tangent of operand 1 into operand 0. Both operands
1 have mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'expM2'
1 Raise e (the base of natural logarithms) to the power of operand 1
1 and store the result in operand 0. Both operands have mode M,
1 which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'expm1M2'
1 Raise e (the base of natural logarithms) to the power of operand 1,
1 subtract 1, and store the result in operand 0. Both operands have
1 mode M, which is a scalar or vector floating-point mode.
1
1 For inputs close to zero, the pattern is expected to be more
1 accurate than a separate 'expM2' and 'subM3' would be.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'exp10M2'
1 Raise 10 to the power of operand 1 and store the result in operand
1 0. Both operands have mode M, which is a scalar or vector
1 floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'exp2M2'
1 Raise 2 to the power of operand 1 and store the result in operand
1 0. Both operands have mode M, which is a scalar or vector
1 floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'logM2'
1 Store the natural logarithm of operand 1 into operand 0. Both
1 operands have mode M, which is a scalar or vector floating-point
1 mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'log1pM2'
1 Add 1 to operand 1, compute the natural logarithm, and store the
1 result in operand 0. Both operands have mode M, which is a scalar
1 or vector floating-point mode.
1
1 For inputs close to zero, the pattern is expected to be more
1 accurate than a separate 'addM3' and 'logM2' would be.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'log10M2'
1 Store the base-10 logarithm of operand 1 into operand 0. Both
1 operands have mode M, which is a scalar or vector floating-point
1 mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'log2M2'
1 Store the base-2 logarithm of operand 1 into operand 0. Both
1 operands have mode M, which is a scalar or vector floating-point
1 mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'logbM2'
1 Store the base-'FLT_RADIX' logarithm of operand 1 into operand 0.
1 Both operands have mode M, which is a scalar or vector
1 floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'significandM2'
1 Store the significand of floating-point operand 1 in operand 0.
1 Both operands have mode M, which is a scalar or vector
1 floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'powM3'
1 Store the value of operand 1 raised to the exponent operand 2 into
1 operand 0. All operands have mode M, which is a scalar or vector
1 floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'atan2M3'
1 Store the arc tangent (inverse tangent) of operand 1 divided by
1 operand 2 into operand 0, using the signs of both arguments to
1 determine the quadrant of the result. All operands have mode M,
1 which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'floorM2'
1 Store the largest integral value not greater than operand 1 in
1 operand 0. Both operands have mode M, which is a scalar or vector
1 floating-point mode. If '-ffp-int-builtin-inexact' is in effect,
1 the "inexact" exception may be raised for noninteger operands;
1 otherwise, it may not.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'btruncM2'
1 Round operand 1 to an integer, towards zero, and store the result
1 in operand 0. Both operands have mode M, which is a scalar or
1 vector floating-point mode. If '-ffp-int-builtin-inexact' is in
1 effect, the "inexact" exception may be raised for noninteger
1 operands; otherwise, it may not.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'roundM2'
1 Round operand 1 to the nearest integer, rounding away from zero in
1 the event of a tie, and store the result in operand 0. Both
1 operands have mode M, which is a scalar or vector floating-point
1 mode. If '-ffp-int-builtin-inexact' is in effect, the "inexact"
1 exception may be raised for noninteger operands; otherwise, it may
1 not.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'ceilM2'
1 Store the smallest integral value not less than operand 1 in
1 operand 0. Both operands have mode M, which is a scalar or vector
1 floating-point mode. If '-ffp-int-builtin-inexact' is in effect,
1 the "inexact" exception may be raised for noninteger operands;
1 otherwise, it may not.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'nearbyintM2'
1 Round operand 1 to an integer, using the current rounding mode, and
1 store the result in operand 0. Do not raise an inexact condition
1 when the result is different from the argument. Both operands have
1 mode M, which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'rintM2'
1 Round operand 1 to an integer, using the current rounding mode, and
1 store the result in operand 0. Raise an inexact condition when the
1 result is different from the argument. Both operands have mode M,
1 which is a scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'lrintMN2'
1 Convert operand 1 (valid for floating point mode M) to fixed point
1 mode N as a signed number according to the current rounding mode
1 and store in operand 0 (which has mode N).
1
1 'lroundMN2'
1 Convert operand 1 (valid for floating point mode M) to fixed point
1 mode N as a signed number rounding to nearest and away from zero
1 and store in operand 0 (which has mode N).
1
1 'lfloorMN2'
1 Convert operand 1 (valid for floating point mode M) to fixed point
1 mode N as a signed number rounding down and store in operand 0
1 (which has mode N).
1
1 'lceilMN2'
1 Convert operand 1 (valid for floating point mode M) to fixed point
1 mode N as a signed number rounding up and store in operand 0 (which
1 has mode N).
1
1 'copysignM3'
1 Store a value with the magnitude of operand 1 and the sign of
1 operand 2 into operand 0. All operands have mode M, which is a
1 scalar or vector floating-point mode.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'ffsM2'
1 Store into operand 0 one plus the index of the least significant
1 1-bit of operand 1. If operand 1 is zero, store zero.
1
1 M is either a scalar or vector integer mode. When it is a scalar,
1 operand 1 has mode M but operand 0 can have whatever scalar integer
1 mode is suitable for the target. The compiler will insert
1 conversion instructions as necessary (typically to convert the
1 result to the same width as 'int'). When M is a vector, both
1 operands must have mode M.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'clrsbM2'
1 Count leading redundant sign bits. Store into operand 0 the number
1 of redundant sign bits in operand 1, starting at the most
1 significant bit position. A redundant sign bit is defined as any
1 sign bit after the first. As such, this count will be one less
1 than the count of leading sign bits.
1
1 M is either a scalar or vector integer mode. When it is a scalar,
1 operand 1 has mode M but operand 0 can have whatever scalar integer
1 mode is suitable for the target. The compiler will insert
1 conversion instructions as necessary (typically to convert the
1 result to the same width as 'int'). When M is a vector, both
1 operands must have mode M.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'clzM2'
1 Store into operand 0 the number of leading 0-bits in operand 1,
1 starting at the most significant bit position. If operand 1 is 0,
1 the 'CLZ_DEFINED_VALUE_AT_ZERO' (⇒Misc) macro defines if the
1 result is undefined or has a useful value.
1
1 M is either a scalar or vector integer mode. When it is a scalar,
1 operand 1 has mode M but operand 0 can have whatever scalar integer
1 mode is suitable for the target. The compiler will insert
1 conversion instructions as necessary (typically to convert the
1 result to the same width as 'int'). When M is a vector, both
1 operands must have mode M.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'ctzM2'
1 Store into operand 0 the number of trailing 0-bits in operand 1,
1 starting at the least significant bit position. If operand 1 is 0,
1 the 'CTZ_DEFINED_VALUE_AT_ZERO' (⇒Misc) macro defines if the
1 result is undefined or has a useful value.
1
1 M is either a scalar or vector integer mode. When it is a scalar,
1 operand 1 has mode M but operand 0 can have whatever scalar integer
1 mode is suitable for the target. The compiler will insert
1 conversion instructions as necessary (typically to convert the
1 result to the same width as 'int'). When M is a vector, both
1 operands must have mode M.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'popcountM2'
1 Store into operand 0 the number of 1-bits in operand 1.
1
1 M is either a scalar or vector integer mode. When it is a scalar,
1 operand 1 has mode M but operand 0 can have whatever scalar integer
1 mode is suitable for the target. The compiler will insert
1 conversion instructions as necessary (typically to convert the
1 result to the same width as 'int'). When M is a vector, both
1 operands must have mode M.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'parityM2'
1 Store into operand 0 the parity of operand 1, i.e. the number of
1 1-bits in operand 1 modulo 2.
1
1 M is either a scalar or vector integer mode. When it is a scalar,
1 operand 1 has mode M but operand 0 can have whatever scalar integer
1 mode is suitable for the target. The compiler will insert
1 conversion instructions as necessary (typically to convert the
1 result to the same width as 'int'). When M is a vector, both
1 operands must have mode M.
1
1 This pattern is not allowed to 'FAIL'.
1
1 'one_cmplM2'
1 Store the bitwise-complement of operand 1 into operand 0.
1
1 'movmemM'
1 Block move instruction. The destination and source blocks of
1 memory are the first two operands, and both are 'mem:BLK's with an
1 address in mode 'Pmode'.
1
1 The number of bytes to move is the third operand, in mode M.
1 Usually, you specify 'Pmode' for M. However, if you can generate
1 better code knowing the range of valid lengths is smaller than
1 those representable in a full Pmode pointer, you should provide a
1 pattern with a mode corresponding to the range of values you can
1 handle efficiently (e.g., 'QImode' for values in the range 0-127;
1 note we avoid numbers that appear negative) and also a pattern with
1 'Pmode'.
1
1 The fourth operand is the known shared alignment of the source and
1 destination, in the form of a 'const_int' rtx. Thus, if the
1 compiler knows that both source and destination are word-aligned,
1 it may provide the value 4 for this operand.
1
1 Optional operands 5 and 6 specify expected alignment and size of
1 block respectively. The expected alignment differs from alignment
1 in operand 4 in a way that the blocks are not required to be
1 aligned according to it in all cases. This expected alignment is
1 also in bytes, just like operand 4. Expected size, when unknown,
1 is set to '(const_int -1)'.
1
1 Descriptions of multiple 'movmemM' patterns can only be beneficial
1 if the patterns for smaller modes have fewer restrictions on their
1 first, second and fourth operands. Note that the mode M in
1 'movmemM' does not impose any restriction on the mode of
1 individually moved data units in the block.
1
1 These patterns need not give special consideration to the
1 possibility that the source and destination strings might overlap.
1
1 'movstr'
1 String copy instruction, with 'stpcpy' semantics. Operand 0 is an
1 output operand in mode 'Pmode'. The addresses of the destination
1 and source strings are operands 1 and 2, and both are 'mem:BLK's
1 with addresses in mode 'Pmode'. The execution of the expansion of
1 this pattern should store in operand 0 the address in which the
1 'NUL' terminator was stored in the destination string.
1
1 This patern has also several optional operands that are same as in
1 'setmem'.
1
1 'setmemM'
1 Block set instruction. The destination string is the first
1 operand, given as a 'mem:BLK' whose address is in mode 'Pmode'.
1 The number of bytes to set is the second operand, in mode M. The
1 value to initialize the memory with is the third operand. Targets
1 that only support the clearing of memory should reject any value
1 that is not the constant 0. See 'movmemM' for a discussion of the
1 choice of mode.
1
1 The fourth operand is the known alignment of the destination, in
1 the form of a 'const_int' rtx. Thus, if the compiler knows that
1 the destination is word-aligned, it may provide the value 4 for
1 this operand.
1
1 Optional operands 5 and 6 specify expected alignment and size of
1 block respectively. The expected alignment differs from alignment
1 in operand 4 in a way that the blocks are not required to be
1 aligned according to it in all cases. This expected alignment is
1 also in bytes, just like operand 4. Expected size, when unknown,
1 is set to '(const_int -1)'. Operand 7 is the minimal size of the
1 block and operand 8 is the maximal size of the block (NULL if it
1 can not be represented as CONST_INT). Operand 9 is the probable
1 maximal size (i.e. we can not rely on it for correctness, but it
1 can be used for choosing proper code sequence for a given size).
1
1 The use for multiple 'setmemM' is as for 'movmemM'.
1
1 'cmpstrnM'
1 String compare instruction, with five operands. Operand 0 is the
1 output; it has mode M. The remaining four operands are like the
1 operands of 'movmemM'. The two memory blocks specified are
1 compared byte by byte in lexicographic order starting at the
1 beginning of each string. The instruction is not allowed to
1 prefetch more than one byte at a time since either string may end
1 in the first byte and reading past that may access an invalid page
1 or segment and cause a fault. The comparison terminates early if
1 the fetched bytes are different or if they are equal to zero. The
1 effect of the instruction is to store a value in operand 0 whose
1 sign indicates the result of the comparison.
1
1 'cmpstrM'
1 String compare instruction, without known maximum length. Operand
1 0 is the output; it has mode M. The second and third operand are
1 the blocks of memory to be compared; both are 'mem:BLK' with an
1 address in mode 'Pmode'.
1
1 The fourth operand is the known shared alignment of the source and
1 destination, in the form of a 'const_int' rtx. Thus, if the
1 compiler knows that both source and destination are word-aligned,
1 it may provide the value 4 for this operand.
1
1 The two memory blocks specified are compared byte by byte in
1 lexicographic order starting at the beginning of each string. The
1 instruction is not allowed to prefetch more than one byte at a time
1 since either string may end in the first byte and reading past that
1 may access an invalid page or segment and cause a fault. The
1 comparison will terminate when the fetched bytes are different or
1 if they are equal to zero. The effect of the instruction is to
1 store a value in operand 0 whose sign indicates the result of the
1 comparison.
1
1 'cmpmemM'
1 Block compare instruction, with five operands like the operands of
1 'cmpstrM'. The two memory blocks specified are compared byte by
1 byte in lexicographic order starting at the beginning of each
1 block. Unlike 'cmpstrM' the instruction can prefetch any bytes in
1 the two memory blocks. Also unlike 'cmpstrM' the comparison will
1 not stop if both bytes are zero. The effect of the instruction is
1 to store a value in operand 0 whose sign indicates the result of
1 the comparison.
1
1 'strlenM'
1 Compute the length of a string, with three operands. Operand 0 is
1 the result (of mode M), operand 1 is a 'mem' referring to the first
1 character of the string, operand 2 is the character to search for
1 (normally zero), and operand 3 is a constant describing the known
1 alignment of the beginning of the string.
1
1 'floatMN2'
1 Convert signed integer operand 1 (valid for fixed point mode M) to
1 floating point mode N and store in operand 0 (which has mode N).
1
1 'floatunsMN2'
1 Convert unsigned integer operand 1 (valid for fixed point mode M)
1 to floating point mode N and store in operand 0 (which has mode N).
1
1 'fixMN2'
1 Convert operand 1 (valid for floating point mode M) to fixed point
1 mode N as a signed number and store in operand 0 (which has mode
1 N). This instruction's result is defined only when the value of
1 operand 1 is an integer.
1
1 If the machine description defines this pattern, it also needs to
1 define the 'ftrunc' pattern.
1
1 'fixunsMN2'
1 Convert operand 1 (valid for floating point mode M) to fixed point
1 mode N as an unsigned number and store in operand 0 (which has mode
1 N). This instruction's result is defined only when the value of
1 operand 1 is an integer.
1
1 'ftruncM2'
1 Convert operand 1 (valid for floating point mode M) to an integer
1 value, still represented in floating point mode M, and store it in
1 operand 0 (valid for floating point mode M).
1
1 'fix_truncMN2'
1 Like 'fixMN2' but works for any floating point value of mode M by
1 converting the value to an integer.
1
1 'fixuns_truncMN2'
1 Like 'fixunsMN2' but works for any floating point value of mode M
1 by converting the value to an integer.
1
1 'truncMN2'
1 Truncate operand 1 (valid for mode M) to mode N and store in
1 operand 0 (which has mode N). Both modes must be fixed point or
1 both floating point.
1
1 'extendMN2'
1 Sign-extend operand 1 (valid for mode M) to mode N and store in
1 operand 0 (which has mode N). Both modes must be fixed point or
1 both floating point.
1
1 'zero_extendMN2'
1 Zero-extend operand 1 (valid for mode M) to mode N and store in
1 operand 0 (which has mode N). Both modes must be fixed point.
1
1 'fractMN2'
1 Convert operand 1 of mode M to mode N and store in operand 0 (which
1 has mode N). Mode M and mode N could be fixed-point to
1 fixed-point, signed integer to fixed-point, fixed-point to signed
1 integer, floating-point to fixed-point, or fixed-point to
1 floating-point. When overflows or underflows happen, the results
1 are undefined.
1
1 'satfractMN2'
1 Convert operand 1 of mode M to mode N and store in operand 0 (which
1 has mode N). Mode M and mode N could be fixed-point to
1 fixed-point, signed integer to fixed-point, or floating-point to
1 fixed-point. When overflows or underflows happen, the instruction
1 saturates the results to the maximum or the minimum.
1
1 'fractunsMN2'
1 Convert operand 1 of mode M to mode N and store in operand 0 (which
1 has mode N). Mode M and mode N could be unsigned integer to
1 fixed-point, or fixed-point to unsigned integer. When overflows or
1 underflows happen, the results are undefined.
1
1 'satfractunsMN2'
1 Convert unsigned integer operand 1 of mode M to fixed-point mode N
1 and store in operand 0 (which has mode N). When overflows or
1 underflows happen, the instruction saturates the results to the
1 maximum or the minimum.
1
1 'extvM'
1 Extract a bit-field from register operand 1, sign-extend it, and
1 store it in operand 0. Operand 2 specifies the width of the field
1 in bits and operand 3 the starting bit, which counts from the most
1 significant bit if 'BITS_BIG_ENDIAN' is true and from the least
1 significant bit otherwise.
1
1 Operands 0 and 1 both have mode M. Operands 2 and 3 have a
1 target-specific mode.
1
1 'extvmisalignM'
1 Extract a bit-field from memory operand 1, sign extend it, and
1 store it in operand 0. Operand 2 specifies the width in bits and
1 operand 3 the starting bit. The starting bit is always somewhere
1 in the first byte of operand 1; it counts from the most significant
1 bit if 'BITS_BIG_ENDIAN' is true and from the least significant bit
1 otherwise.
1
1 Operand 0 has mode M while operand 1 has 'BLK' mode. Operands 2
1 and 3 have a target-specific mode.
1
1 The instruction must not read beyond the last byte of the
1 bit-field.
1
1 'extzvM'
1 Like 'extvM' except that the bit-field value is zero-extended.
1
1 'extzvmisalignM'
1 Like 'extvmisalignM' except that the bit-field value is
1 zero-extended.
1
1 'insvM'
1 Insert operand 3 into a bit-field of register operand 0. Operand 1
1 specifies the width of the field in bits and operand 2 the starting
1 bit, which counts from the most significant bit if
1 'BITS_BIG_ENDIAN' is true and from the least significant bit
1 otherwise.
1
1 Operands 0 and 3 both have mode M. Operands 1 and 2 have a
1 target-specific mode.
1
1 'insvmisalignM'
1 Insert operand 3 into a bit-field of memory operand 0. Operand 1
1 specifies the width of the field in bits and operand 2 the starting
1 bit. The starting bit is always somewhere in the first byte of
1 operand 0; it counts from the most significant bit if
1 'BITS_BIG_ENDIAN' is true and from the least significant bit
1 otherwise.
1
1 Operand 3 has mode M while operand 0 has 'BLK' mode. Operands 1
1 and 2 have a target-specific mode.
1
1 The instruction must not read or write beyond the last byte of the
1 bit-field.
1
1 'extv'
1 Extract a bit-field from operand 1 (a register or memory operand),
1 where operand 2 specifies the width in bits and operand 3 the
1 starting bit, and store it in operand 0. Operand 0 must have mode
1 'word_mode'. Operand 1 may have mode 'byte_mode' or 'word_mode';
1 often 'word_mode' is allowed only for registers. Operands 2 and 3
1 must be valid for 'word_mode'.
1
1 The RTL generation pass generates this instruction only with
1 constants for operands 2 and 3 and the constant is never zero for
1 operand 2.
1
1 The bit-field value is sign-extended to a full word integer before
1 it is stored in operand 0.
1
1 This pattern is deprecated; please use 'extvM' and 'extvmisalignM'
1 instead.
1
1 'extzv'
1 Like 'extv' except that the bit-field value is zero-extended.
1
1 This pattern is deprecated; please use 'extzvM' and
1 'extzvmisalignM' instead.
1
1 'insv'
1 Store operand 3 (which must be valid for 'word_mode') into a
1 bit-field in operand 0, where operand 1 specifies the width in bits
1 and operand 2 the starting bit. Operand 0 may have mode
1 'byte_mode' or 'word_mode'; often 'word_mode' is allowed only for
1 registers. Operands 1 and 2 must be valid for 'word_mode'.
1
1 The RTL generation pass generates this instruction only with
1 constants for operands 1 and 2 and the constant is never zero for
1 operand 1.
1
1 This pattern is deprecated; please use 'insvM' and 'insvmisalignM'
1 instead.
1
1 'movMODEcc'
1 Conditionally move operand 2 or operand 3 into operand 0 according
1 to the comparison in operand 1. If the comparison is true, operand
1 2 is moved into operand 0, otherwise operand 3 is moved.
1
1 The mode of the operands being compared need not be the same as the
1 operands being moved. Some machines, sparc64 for example, have
1 instructions that conditionally move an integer value based on the
1 floating point condition codes and vice versa.
1
1 If the machine does not have conditional move instructions, do not
1 define these patterns.
1
1 'addMODEcc'
1 Similar to 'movMODEcc' but for conditional addition. Conditionally
1 move operand 2 or (operands 2 + operand 3) into operand 0 according
1 to the comparison in operand 1. If the comparison is false,
1 operand 2 is moved into operand 0, otherwise (operand 2 + operand
1 3) is moved.
1
1 'cond_addMODE'
1 'cond_subMODE'
1 'cond_andMODE'
1 'cond_iorMODE'
1 'cond_xorMODE'
1 'cond_sminMODE'
1 'cond_smaxMODE'
1 'cond_uminMODE'
1 'cond_umaxMODE'
1 Perform an elementwise operation on vector operands 2 and 3, under
1 the control of the vector mask in operand 1, and store the result
1 in operand 0. This is equivalent to:
1
1 for (i = 0; i < GET_MODE_NUNITS (N); i++)
1 op0[i] = op1[i] ? op2[i] OP op3[i] : op2[i];
1
1 where, for example, OP is '+' for 'cond_addMODE'.
1
1 When defined for floating-point modes, the contents of 'op3[i]' are
1 not interpreted if OP1[I] is false, just like they would not be in
1 a normal C '?:' condition.
1
1 Operands 0, 2 and 3 all have mode M, while operand 1 has the mode
1 returned by 'TARGET_VECTORIZE_GET_MASK_MODE'.
1
1 'negMODEcc'
1 Similar to 'movMODEcc' but for conditional negation. Conditionally
1 move the negation of operand 2 or the unchanged operand 3 into
1 operand 0 according to the comparison in operand 1. If the
1 comparison is true, the negation of operand 2 is moved into operand
1 0, otherwise operand 3 is moved.
1
1 'notMODEcc'
1 Similar to 'negMODEcc' but for conditional complement.
1 Conditionally move the bitwise complement of operand 2 or the
1 unchanged operand 3 into operand 0 according to the comparison in
1 operand 1. If the comparison is true, the complement of operand 2
1 is moved into operand 0, otherwise operand 3 is moved.
1
1 'cstoreMODE4'
1 Store zero or nonzero in operand 0 according to whether a
1 comparison is true. Operand 1 is a comparison operator. Operand 2
1 and operand 3 are the first and second operand of the comparison,
1 respectively. You specify the mode that operand 0 must have when
1 you write the 'match_operand' expression. The compiler
1 automatically sees which mode you have used and supplies an operand
1 of that mode.
1
1 The value stored for a true condition must have 1 as its low bit,
1 or else must be negative. Otherwise the instruction is not
1 suitable and you should omit it from the machine description. You
1 describe to the compiler exactly which value is stored by defining
1 the macro 'STORE_FLAG_VALUE' (⇒Misc). If a description
1 cannot be found that can be used for all the possible comparison
1 operators, you should pick one and use a 'define_expand' to map all
1 results onto the one you chose.
1
1 These operations may 'FAIL', but should do so only in relatively
1 uncommon cases; if they would 'FAIL' for common cases involving
1 integer comparisons, it is best to restrict the predicates to not
1 allow these operands. Likewise if a given comparison operator will
1 always fail, independent of the operands (for floating-point modes,
1 the 'ordered_comparison_operator' predicate is often useful in this
1 case).
1
1 If this pattern is omitted, the compiler will generate a
1 conditional branch--for example, it may copy a constant one to the
1 target and branching around an assignment of zero to the target--or
1 a libcall. If the predicate for operand 1 only rejects some
1 operators, it will also try reordering the operands and/or
1 inverting the result value (e.g. by an exclusive OR). These
1 possibilities could be cheaper or equivalent to the instructions
1 used for the 'cstoreMODE4' pattern followed by those required to
1 convert a positive result from 'STORE_FLAG_VALUE' to 1; in this
1 case, you can and should make operand 1's predicate reject some
1 operators in the 'cstoreMODE4' pattern, or remove the pattern
1 altogether from the machine description.
1
1 'cbranchMODE4'
1 Conditional branch instruction combined with a compare instruction.
1 Operand 0 is a comparison operator. Operand 1 and operand 2 are
1 the first and second operands of the comparison, respectively.
1 Operand 3 is the 'code_label' to jump to.
1
1 'jump'
1 A jump inside a function; an unconditional branch. Operand 0 is
1 the 'code_label' to jump to. This pattern name is mandatory on all
1 machines.
1
1 'call'
1 Subroutine call instruction returning no value. Operand 0 is the
1 function to call; operand 1 is the number of bytes of arguments
1 pushed as a 'const_int'; operand 2 is the number of registers used
1 as operands.
1
1 On most machines, operand 2 is not actually stored into the RTL
1 pattern. It is supplied for the sake of some RISC machines which
1 need to put this information into the assembler code; they can put
1 it in the RTL instead of operand 1.
1
1 Operand 0 should be a 'mem' RTX whose address is the address of the
1 function. Note, however, that this address can be a 'symbol_ref'
1 expression even if it would not be a legitimate memory address on
1 the target machine. If it is also not a valid argument for a call
1 instruction, the pattern for this operation should be a
1 'define_expand' (⇒Expander Definitions) that places the
1 address into a register and uses that register in the call
1 instruction.
1
1 'call_value'
1 Subroutine call instruction returning a value. Operand 0 is the
1 hard register in which the value is returned. There are three more
1 operands, the same as the three operands of the 'call' instruction
1 (but with numbers increased by one).
1
1 Subroutines that return 'BLKmode' objects use the 'call' insn.
1
1 'call_pop', 'call_value_pop'
1 Similar to 'call' and 'call_value', except used if defined and if
1 'RETURN_POPS_ARGS' is nonzero. They should emit a 'parallel' that
1 contains both the function call and a 'set' to indicate the
1 adjustment made to the frame pointer.
1
1 For machines where 'RETURN_POPS_ARGS' can be nonzero, the use of
1 these patterns increases the number of functions for which the
1 frame pointer can be eliminated, if desired.
1
1 'untyped_call'
1 Subroutine call instruction returning a value of any type. Operand
1 0 is the function to call; operand 1 is a memory location where the
1 result of calling the function is to be stored; operand 2 is a
1 'parallel' expression where each element is a 'set' expression that
1 indicates the saving of a function return value into the result
1 block.
1
1 This instruction pattern should be defined to support
1 '__builtin_apply' on machines where special instructions are needed
1 to call a subroutine with arbitrary arguments or to save the value
1 returned. This instruction pattern is required on machines that
1 have multiple registers that can hold a return value (i.e.
1 'FUNCTION_VALUE_REGNO_P' is true for more than one register).
1
1 'return'
1 Subroutine return instruction. This instruction pattern name
1 should be defined only if a single instruction can do all the work
1 of returning from a function.
1
1 Like the 'movM' patterns, this pattern is also used after the RTL
1 generation phase. In this case it is to support machines where
1 multiple instructions are usually needed to return from a function,
1 but some class of functions only requires one instruction to
1 implement a return. Normally, the applicable functions are those
1 which do not need to save any registers or allocate stack space.
1
1 It is valid for this pattern to expand to an instruction using
1 'simple_return' if no epilogue is required.
1
1 'simple_return'
1 Subroutine return instruction. This instruction pattern name
1 should be defined only if a single instruction can do all the work
1 of returning from a function on a path where no epilogue is
1 required. This pattern is very similar to the 'return' instruction
1 pattern, but it is emitted only by the shrink-wrapping optimization
1 on paths where the function prologue has not been executed, and a
1 function return should occur without any of the effects of the
1 epilogue. Additional uses may be introduced on paths where both
1 the prologue and the epilogue have executed.
1
1 For such machines, the condition specified in this pattern should
1 only be true when 'reload_completed' is nonzero and the function's
1 epilogue would only be a single instruction. For machines with
1 register windows, the routine 'leaf_function_p' may be used to
1 determine if a register window push is required.
1
1 Machines that have conditional return instructions should define
1 patterns such as
1
1 (define_insn ""
1 [(set (pc)
1 (if_then_else (match_operator
1 0 "comparison_operator"
1 [(cc0) (const_int 0)])
1 (return)
1 (pc)))]
1 "CONDITION"
1 "...")
1
1 where CONDITION would normally be the same condition specified on
1 the named 'return' pattern.
1
1 'untyped_return'
1 Untyped subroutine return instruction. This instruction pattern
1 should be defined to support '__builtin_return' on machines where
1 special instructions are needed to return a value of any type.
1
1 Operand 0 is a memory location where the result of calling a
1 function with '__builtin_apply' is stored; operand 1 is a
1 'parallel' expression where each element is a 'set' expression that
1 indicates the restoring of a function return value from the result
1 block.
1
1 'nop'
1 No-op instruction. This instruction pattern name should always be
1 defined to output a no-op in assembler code. '(const_int 0)' will
1 do as an RTL pattern.
1
1 'indirect_jump'
1 An instruction to jump to an address which is operand zero. This
1 pattern name is mandatory on all machines.
1
1 'casesi'
1 Instruction to jump through a dispatch table, including bounds
1 checking. This instruction takes five operands:
1
1 1. The index to dispatch on, which has mode 'SImode'.
1
1 2. The lower bound for indices in the table, an integer constant.
1
1 3. The total range of indices in the table--the largest index
1 minus the smallest one (both inclusive).
1
1 4. A label that precedes the table itself.
1
1 5. A label to jump to if the index has a value outside the
1 bounds.
1
1 The table is an 'addr_vec' or 'addr_diff_vec' inside of a
1 'jump_table_data'. The number of elements in the table is one plus
1 the difference between the upper bound and the lower bound.
1
1 'tablejump'
1 Instruction to jump to a variable address. This is a low-level
1 capability which can be used to implement a dispatch table when
1 there is no 'casesi' pattern.
1
1 This pattern requires two operands: the address or offset, and a
1 label which should immediately precede the jump table. If the
1 macro 'CASE_VECTOR_PC_RELATIVE' evaluates to a nonzero value then
1 the first operand is an offset which counts from the address of the
1 table; otherwise, it is an absolute address to jump to. In either
1 case, the first operand has mode 'Pmode'.
1
1 The 'tablejump' insn is always the last insn before the jump table
1 it uses. Its assembler code normally has no need to use the second
1 operand, but you should incorporate it in the RTL pattern so that
1 the jump optimizer will not delete the table as unreachable code.
1
1 'decrement_and_branch_until_zero'
1 Conditional branch instruction that decrements a register and jumps
1 if the register is nonzero. Operand 0 is the register to decrement
1 and test; operand 1 is the label to jump to if the register is
1 nonzero. ⇒Looping Patterns.
1
1 This optional instruction pattern is only used by the combiner,
1 typically for loops reversed by the loop optimizer when strength
1 reduction is enabled.
1
1 'doloop_end'
1 Conditional branch instruction that decrements a register and jumps
1 if the register is nonzero. Operand 0 is the register to decrement
1 and test; operand 1 is the label to jump to if the register is
1 nonzero. ⇒Looping Patterns.
1
1 This optional instruction pattern should be defined for machines
1 with low-overhead looping instructions as the loop optimizer will
1 try to modify suitable loops to utilize it. The target hook
1 'TARGET_CAN_USE_DOLOOP_P' controls the conditions under which
1 low-overhead loops can be used.
1
1 'doloop_begin'
1 Companion instruction to 'doloop_end' required for machines that
1 need to perform some initialization, such as loading a special
1 counter register. Operand 1 is the associated 'doloop_end' pattern
1 and operand 0 is the register that it decrements.
1
1 If initialization insns do not always need to be emitted, use a
1 'define_expand' (⇒Expander Definitions) and make it fail.
1
1 'canonicalize_funcptr_for_compare'
1 Canonicalize the function pointer in operand 1 and store the result
1 into operand 0.
1
1 Operand 0 is always a 'reg' and has mode 'Pmode'; operand 1 may be
1 a 'reg', 'mem', 'symbol_ref', 'const_int', etc and also has mode
1 'Pmode'.
1
1 Canonicalization of a function pointer usually involves computing
1 the address of the function which would be called if the function
1 pointer were used in an indirect call.
1
1 Only define this pattern if function pointers on the target machine
1 can have different values but still call the same function when
1 used in an indirect call.
1
1 'save_stack_block'
1 'save_stack_function'
1 'save_stack_nonlocal'
1 'restore_stack_block'
1 'restore_stack_function'
1 'restore_stack_nonlocal'
1 Most machines save and restore the stack pointer by copying it to
1 or from an object of mode 'Pmode'. Do not define these patterns on
1 such machines.
1
1 Some machines require special handling for stack pointer saves and
1 restores. On those machines, define the patterns corresponding to
11 the non-standard cases by using a 'define_expand' (⇒Expander
Definitions) that produces the required insns. The three types
1 of saves and restores are:
1
1 1. 'save_stack_block' saves the stack pointer at the start of a
1 block that allocates a variable-sized object, and
1 'restore_stack_block' restores the stack pointer when the
1 block is exited.
1
1 2. 'save_stack_function' and 'restore_stack_function' do a
1 similar job for the outermost block of a function and are used
1 when the function allocates variable-sized objects or calls
1 'alloca'. Only the epilogue uses the restored stack pointer,
1 allowing a simpler save or restore sequence on some machines.
1
1 3. 'save_stack_nonlocal' is used in functions that contain labels
1 branched to by nested functions. It saves the stack pointer
1 in such a way that the inner function can use
1 'restore_stack_nonlocal' to restore the stack pointer. The
1 compiler generates code to restore the frame and argument
1 pointer registers, but some machines require saving and
1 restoring additional data such as register window information
1 or stack backchains. Place insns in these patterns to save
1 and restore any such required data.
1
1 When saving the stack pointer, operand 0 is the save area and
1 operand 1 is the stack pointer. The mode used to allocate the save
1 area defaults to 'Pmode' but you can override that choice by
1 defining the 'STACK_SAVEAREA_MODE' macro (⇒Storage Layout).
1 You must specify an integral mode, or 'VOIDmode' if no save area is
1 needed for a particular type of save (either because no save is
1 needed or because a machine-specific save area can be used).
1 Operand 0 is the stack pointer and operand 1 is the save area for
1 restore operations. If 'save_stack_block' is defined, operand 0
1 must not be 'VOIDmode' since these saves can be arbitrarily nested.
1
1 A save area is a 'mem' that is at a constant offset from
1 'virtual_stack_vars_rtx' when the stack pointer is saved for use by
1 nonlocal gotos and a 'reg' in the other two cases.
1
1 'allocate_stack'
1 Subtract (or add if 'STACK_GROWS_DOWNWARD' is undefined) operand 1
1 from the stack pointer to create space for dynamically allocated
1 data.
1
1 Store the resultant pointer to this space into operand 0. If you
1 are allocating space from the main stack, do this by emitting a
1 move insn to copy 'virtual_stack_dynamic_rtx' to operand 0. If you
1 are allocating the space elsewhere, generate code to copy the
1 location of the space to operand 0. In the latter case, you must
1 ensure this space gets freed when the corresponding space on the
1 main stack is free.
1
1 Do not define this pattern if all that must be done is the
1 subtraction. Some machines require other operations such as stack
1 probes or maintaining the back chain. Define this pattern to emit
1 those operations in addition to updating the stack pointer.
1
1 'check_stack'
1 If stack checking (⇒Stack Checking) cannot be done on your
1 system by probing the stack, define this pattern to perform the
1 needed check and signal an error if the stack has overflowed. The
1 single operand is the address in the stack farthest from the
1 current stack pointer that you need to validate. Normally, on
1 platforms where this pattern is needed, you would obtain the stack
1 limit from a global or thread-specific variable or register.
1
1 'probe_stack_address'
1 If stack checking (⇒Stack Checking) can be done on your
1 system by probing the stack but without the need to actually access
1 it, define this pattern and signal an error if the stack has
1 overflowed. The single operand is the memory address in the stack
1 that needs to be probed.
1
1 'probe_stack'
1 If stack checking (⇒Stack Checking) can be done on your
1 system by probing the stack but doing it with a "store zero"
1 instruction is not valid or optimal, define this pattern to do the
1 probing differently and signal an error if the stack has
1 overflowed. The single operand is the memory reference in the
1 stack that needs to be probed.
1
1 'nonlocal_goto'
1 Emit code to generate a non-local goto, e.g., a jump from one
1 function to a label in an outer function. This pattern has four
1 arguments, each representing a value to be used in the jump. The
1 first argument is to be loaded into the frame pointer, the second
1 is the address to branch to (code to dispatch to the actual label),
1 the third is the address of a location where the stack is saved,
1 and the last is the address of the label, to be placed in the
1 location for the incoming static chain.
1
1 On most machines you need not define this pattern, since GCC will
1 already generate the correct code, which is to load the frame
1 pointer and static chain, restore the stack (using the
1 'restore_stack_nonlocal' pattern, if defined), and jump indirectly
1 to the dispatcher. You need only define this pattern if this code
1 will not work on your machine.
1
1 'nonlocal_goto_receiver'
1 This pattern, if defined, contains code needed at the target of a
1 nonlocal goto after the code already generated by GCC. You will
1 not normally need to define this pattern. A typical reason why you
1 might need this pattern is if some value, such as a pointer to a
1 global table, must be restored when the frame pointer is restored.
1 Note that a nonlocal goto only occurs within a unit-of-translation,
1 so a global table pointer that is shared by all functions of a
1 given module need not be restored. There are no arguments.
1
1 'exception_receiver'
1 This pattern, if defined, contains code needed at the site of an
1 exception handler that isn't needed at the site of a nonlocal goto.
1 You will not normally need to define this pattern. A typical
1 reason why you might need this pattern is if some value, such as a
1 pointer to a global table, must be restored after control flow is
1 branched to the handler of an exception. There are no arguments.
1
1 'builtin_setjmp_setup'
1 This pattern, if defined, contains additional code needed to
1 initialize the 'jmp_buf'. You will not normally need to define
1 this pattern. A typical reason why you might need this pattern is
1 if some value, such as a pointer to a global table, must be
1 restored. Though it is preferred that the pointer value be
1 recalculated if possible (given the address of a label for
1 instance). The single argument is a pointer to the 'jmp_buf'.
1 Note that the buffer is five words long and that the first three
1 are normally used by the generic mechanism.
1
1 'builtin_setjmp_receiver'
1 This pattern, if defined, contains code needed at the site of a
1 built-in setjmp that isn't needed at the site of a nonlocal goto.
1 You will not normally need to define this pattern. A typical
1 reason why you might need this pattern is if some value, such as a
1 pointer to a global table, must be restored. It takes one
1 argument, which is the label to which builtin_longjmp transferred
1 control; this pattern may be emitted at a small offset from that
1 label.
1
1 'builtin_longjmp'
1 This pattern, if defined, performs the entire action of the
1 longjmp. You will not normally need to define this pattern unless
1 you also define 'builtin_setjmp_setup'. The single argument is a
1 pointer to the 'jmp_buf'.
1
1 'eh_return'
1 This pattern, if defined, affects the way '__builtin_eh_return',
1 and thence the call frame exception handling library routines, are
1 built. It is intended to handle non-trivial actions needed along
1 the abnormal return path.
1
1 The address of the exception handler to which the function should
1 return is passed as operand to this pattern. It will normally need
1 to copied by the pattern to some special register or memory
1 location. If the pattern needs to determine the location of the
1 target call frame in order to do so, it may use
1 'EH_RETURN_STACKADJ_RTX', if defined; it will have already been
1 assigned.
1
1 If this pattern is not defined, the default action will be to
1 simply copy the return address to 'EH_RETURN_HANDLER_RTX'. Either
1 that macro or this pattern needs to be defined if call frame
1 exception handling is to be used.
1
1 'prologue'
1 This pattern, if defined, emits RTL for entry to a function. The
1 function entry is responsible for setting up the stack frame,
1 initializing the frame pointer register, saving callee saved
1 registers, etc.
1
1 Using a prologue pattern is generally preferred over defining
1 'TARGET_ASM_FUNCTION_PROLOGUE' to emit assembly code for the
1 prologue.
1
1 The 'prologue' pattern is particularly useful for targets which
1 perform instruction scheduling.
1
1 'window_save'
1 This pattern, if defined, emits RTL for a register window save. It
1 should be defined if the target machine has register windows but
1 the window events are decoupled from calls to subroutines. The
1 canonical example is the SPARC architecture.
1
1 'epilogue'
1 This pattern emits RTL for exit from a function. The function exit
1 is responsible for deallocating the stack frame, restoring callee
1 saved registers and emitting the return instruction.
1
1 Using an epilogue pattern is generally preferred over defining
1 'TARGET_ASM_FUNCTION_EPILOGUE' to emit assembly code for the
1 epilogue.
1
1 The 'epilogue' pattern is particularly useful for targets which
1 perform instruction scheduling or which have delay slots for their
1 return instruction.
1
1 'sibcall_epilogue'
1 This pattern, if defined, emits RTL for exit from a function
1 without the final branch back to the calling function. This
1 pattern will be emitted before any sibling call (aka tail call)
1 sites.
1
1 The 'sibcall_epilogue' pattern must not clobber any arguments used
1 for parameter passing or any stack slots for arguments passed to
1 the current function.
1
1 'trap'
1 This pattern, if defined, signals an error, typically by causing
1 some kind of signal to be raised.
1
1 'ctrapMM4'
1 Conditional trap instruction. Operand 0 is a piece of RTL which
1 performs a comparison, and operands 1 and 2 are the arms of the
1 comparison. Operand 3 is the trap code, an integer.
1
1 A typical 'ctrap' pattern looks like
1
1 (define_insn "ctrapsi4"
1 [(trap_if (match_operator 0 "trap_operator"
1 [(match_operand 1 "register_operand")
1 (match_operand 2 "immediate_operand")])
1 (match_operand 3 "const_int_operand" "i"))]
1 ""
1 "...")
1
1 'prefetch'
1 This pattern, if defined, emits code for a non-faulting data
1 prefetch instruction. Operand 0 is the address of the memory to
1 prefetch. Operand 1 is a constant 1 if the prefetch is preparing
1 for a write to the memory address, or a constant 0 otherwise.
1 Operand 2 is the expected degree of temporal locality of the data
1 and is a value between 0 and 3, inclusive; 0 means that the data
1 has no temporal locality, so it need not be left in the cache after
1 the access; 3 means that the data has a high degree of temporal
1 locality and should be left in all levels of cache possible; 1 and
1 2 mean, respectively, a low or moderate degree of temporal
1 locality.
1
1 Targets that do not support write prefetches or locality hints can
1 ignore the values of operands 1 and 2.
1
1 'blockage'
1 This pattern defines a pseudo insn that prevents the instruction
1 scheduler and other passes from moving instructions and using
1 register equivalences across the boundary defined by the blockage
1 insn. This needs to be an UNSPEC_VOLATILE pattern or a volatile
1 ASM.
1
1 'memory_blockage'
1 This pattern, if defined, represents a compiler memory barrier, and
1 will be placed at points across which RTL passes may not propagate
1 memory accesses. This instruction needs to read and write volatile
1 BLKmode memory. It does not need to generate any machine
1 instruction. If this pattern is not defined, the compiler falls
1 back to emitting an instruction corresponding to 'asm volatile (""
1 ::: "memory")'.
1
1 'memory_barrier'
1 If the target memory model is not fully synchronous, then this
1 pattern should be defined to an instruction that orders both loads
1 and stores before the instruction with respect to loads and stores
1 after the instruction. This pattern has no operands.
1
1 'sync_compare_and_swapMODE'
1 This pattern, if defined, emits code for an atomic compare-and-swap
1 operation. Operand 1 is the memory on which the atomic operation
1 is performed. Operand 2 is the "old" value to be compared against
1 the current contents of the memory location. Operand 3 is the
1 "new" value to store in the memory if the compare succeeds.
1 Operand 0 is the result of the operation; it should contain the
1 contents of the memory before the operation. If the compare
1 succeeds, this should obviously be a copy of operand 2.
1
1 This pattern must show that both operand 0 and operand 1 are
1 modified.
1
1 This pattern must issue any memory barrier instructions such that
1 all memory operations before the atomic operation occur before the
1 atomic operation and all memory operations after the atomic
1 operation occur after the atomic operation.
1
1 For targets where the success or failure of the compare-and-swap
1 operation is available via the status flags, it is possible to
1 avoid a separate compare operation and issue the subsequent branch
1 or store-flag operation immediately after the compare-and-swap. To
1 this end, GCC will look for a 'MODE_CC' set in the output of
1 'sync_compare_and_swapMODE'; if the machine description includes
1 such a set, the target should also define special 'cbranchcc4'
1 and/or 'cstorecc4' instructions. GCC will then be able to take the
1 destination of the 'MODE_CC' set and pass it to the 'cbranchcc4' or
1 'cstorecc4' pattern as the first operand of the comparison (the
1 second will be '(const_int 0)').
1
1 For targets where the operating system may provide support for this
1 operation via library calls, the 'sync_compare_and_swap_optab' may
1 be initialized to a function with the same interface as the
1 '__sync_val_compare_and_swap_N' built-in. If the entire set of
1 __SYNC builtins are supported via library calls, the target can
1 initialize all of the optabs at once with 'init_sync_libfuncs'.
1 For the purposes of C++11 'std::atomic::is_lock_free', it is
1 assumed that these library calls do _not_ use any kind of
1 interruptable locking.
1
1 'sync_addMODE', 'sync_subMODE'
1 'sync_iorMODE', 'sync_andMODE'
1 'sync_xorMODE', 'sync_nandMODE'
1 These patterns emit code for an atomic operation on memory.
1 Operand 0 is the memory on which the atomic operation is performed.
1 Operand 1 is the second operand to the binary operator.
1
1 This pattern must issue any memory barrier instructions such that
1 all memory operations before the atomic operation occur before the
1 atomic operation and all memory operations after the atomic
1 operation occur after the atomic operation.
1
1 If these patterns are not defined, the operation will be
1 constructed from a compare-and-swap operation, if defined.
1
1 'sync_old_addMODE', 'sync_old_subMODE'
1 'sync_old_iorMODE', 'sync_old_andMODE'
1 'sync_old_xorMODE', 'sync_old_nandMODE'
1 These patterns emit code for an atomic operation on memory, and
1 return the value that the memory contained before the operation.
1 Operand 0 is the result value, operand 1 is the memory on which the
1 atomic operation is performed, and operand 2 is the second operand
1 to the binary operator.
1
1 This pattern must issue any memory barrier instructions such that
1 all memory operations before the atomic operation occur before the
1 atomic operation and all memory operations after the atomic
1 operation occur after the atomic operation.
1
1 If these patterns are not defined, the operation will be
1 constructed from a compare-and-swap operation, if defined.
1
1 'sync_new_addMODE', 'sync_new_subMODE'
1 'sync_new_iorMODE', 'sync_new_andMODE'
1 'sync_new_xorMODE', 'sync_new_nandMODE'
1 These patterns are like their 'sync_old_OP' counterparts, except
1 that they return the value that exists in the memory location after
1 the operation, rather than before the operation.
1
1 'sync_lock_test_and_setMODE'
1 This pattern takes two forms, based on the capabilities of the
1 target. In either case, operand 0 is the result of the operand,
1 operand 1 is the memory on which the atomic operation is performed,
1 and operand 2 is the value to set in the lock.
1
1 In the ideal case, this operation is an atomic exchange operation,
1 in which the previous value in memory operand is copied into the
1 result operand, and the value operand is stored in the memory
1 operand.
1
1 For less capable targets, any value operand that is not the
1 constant 1 should be rejected with 'FAIL'. In this case the target
1 may use an atomic test-and-set bit operation. The result operand
1 should contain 1 if the bit was previously set and 0 if the bit was
1 previously clear. The true contents of the memory operand are
1 implementation defined.
1
1 This pattern must issue any memory barrier instructions such that
1 the pattern as a whole acts as an acquire barrier, that is all
1 memory operations after the pattern do not occur until the lock is
1 acquired.
1
1 If this pattern is not defined, the operation will be constructed
1 from a compare-and-swap operation, if defined.
1
1 'sync_lock_releaseMODE'
1 This pattern, if defined, releases a lock set by
1 'sync_lock_test_and_setMODE'. Operand 0 is the memory that
1 contains the lock; operand 1 is the value to store in the lock.
1
1 If the target doesn't implement full semantics for
1 'sync_lock_test_and_setMODE', any value operand which is not the
1 constant 0 should be rejected with 'FAIL', and the true contents of
1 the memory operand are implementation defined.
1
1 This pattern must issue any memory barrier instructions such that
1 the pattern as a whole acts as a release barrier, that is the lock
1 is released only after all previous memory operations have
1 completed.
1
1 If this pattern is not defined, then a 'memory_barrier' pattern
1 will be emitted, followed by a store of the value to the memory
1 operand.
1
1 'atomic_compare_and_swapMODE'
1 This pattern, if defined, emits code for an atomic compare-and-swap
1 operation with memory model semantics. Operand 2 is the memory on
1 which the atomic operation is performed. Operand 0 is an output
1 operand which is set to true or false based on whether the
1 operation succeeded. Operand 1 is an output operand which is set
1 to the contents of the memory before the operation was attempted.
1 Operand 3 is the value that is expected to be in memory. Operand 4
1 is the value to put in memory if the expected value is found there.
1 Operand 5 is set to 1 if this compare and swap is to be treated as
1 a weak operation. Operand 6 is the memory model to be used if the
1 operation is a success. Operand 7 is the memory model to be used
1 if the operation fails.
1
1 If memory referred to in operand 2 contains the value in operand 3,
1 then operand 4 is stored in memory pointed to by operand 2 and
1 fencing based on the memory model in operand 6 is issued.
1
1 If memory referred to in operand 2 does not contain the value in
1 operand 3, then fencing based on the memory model in operand 7 is
1 issued.
1
1 If a target does not support weak compare-and-swap operations, or
1 the port elects not to implement weak operations, the argument in
1 operand 5 can be ignored. Note a strong implementation must be
1 provided.
1
1 If this pattern is not provided, the '__atomic_compare_exchange'
1 built-in functions will utilize the legacy 'sync_compare_and_swap'
1 pattern with an '__ATOMIC_SEQ_CST' memory model.
1
1 'atomic_loadMODE'
1 This pattern implements an atomic load operation with memory model
1 semantics. Operand 1 is the memory address being loaded from.
1 Operand 0 is the result of the load. Operand 2 is the memory model
1 to be used for the load operation.
1
1 If not present, the '__atomic_load' built-in function will either
1 resort to a normal load with memory barriers, or a compare-and-swap
1 operation if a normal load would not be atomic.
1
1 'atomic_storeMODE'
1 This pattern implements an atomic store operation with memory model
1 semantics. Operand 0 is the memory address being stored to.
1 Operand 1 is the value to be written. Operand 2 is the memory
1 model to be used for the operation.
1
1 If not present, the '__atomic_store' built-in function will attempt
1 to perform a normal store and surround it with any required memory
1 fences. If the store would not be atomic, then an
1 '__atomic_exchange' is attempted with the result being ignored.
1
1 'atomic_exchangeMODE'
1 This pattern implements an atomic exchange operation with memory
1 model semantics. Operand 1 is the memory location the operation is
1 performed on. Operand 0 is an output operand which is set to the
1 original value contained in the memory pointed to by operand 1.
1 Operand 2 is the value to be stored. Operand 3 is the memory model
1 to be used.
1
1 If this pattern is not present, the built-in function
1 '__atomic_exchange' will attempt to preform the operation with a
1 compare and swap loop.
1
1 'atomic_addMODE', 'atomic_subMODE'
1 'atomic_orMODE', 'atomic_andMODE'
1 'atomic_xorMODE', 'atomic_nandMODE'
1 These patterns emit code for an atomic operation on memory with
1 memory model semantics. Operand 0 is the memory on which the
1 atomic operation is performed. Operand 1 is the second operand to
1 the binary operator. Operand 2 is the memory model to be used by
1 the operation.
1
1 If these patterns are not defined, attempts will be made to use
1 legacy 'sync' patterns, or equivalent patterns which return a
1 result. If none of these are available a compare-and-swap loop
1 will be used.
1
1 'atomic_fetch_addMODE', 'atomic_fetch_subMODE'
1 'atomic_fetch_orMODE', 'atomic_fetch_andMODE'
1 'atomic_fetch_xorMODE', 'atomic_fetch_nandMODE'
1 These patterns emit code for an atomic operation on memory with
1 memory model semantics, and return the original value. Operand 0
1 is an output operand which contains the value of the memory
1 location before the operation was performed. Operand 1 is the
1 memory on which the atomic operation is performed. Operand 2 is
1 the second operand to the binary operator. Operand 3 is the memory
1 model to be used by the operation.
1
1 If these patterns are not defined, attempts will be made to use
1 legacy 'sync' patterns. If none of these are available a
1 compare-and-swap loop will be used.
1
1 'atomic_add_fetchMODE', 'atomic_sub_fetchMODE'
1 'atomic_or_fetchMODE', 'atomic_and_fetchMODE'
1 'atomic_xor_fetchMODE', 'atomic_nand_fetchMODE'
1 These patterns emit code for an atomic operation on memory with
1 memory model semantics and return the result after the operation is
1 performed. Operand 0 is an output operand which contains the value
1 after the operation. Operand 1 is the memory on which the atomic
1 operation is performed. Operand 2 is the second operand to the
1 binary operator. Operand 3 is the memory model to be used by the
1 operation.
1
1 If these patterns are not defined, attempts will be made to use
1 legacy 'sync' patterns, or equivalent patterns which return the
1 result before the operation followed by the arithmetic operation
1 required to produce the result. If none of these are available a
1 compare-and-swap loop will be used.
1
1 'atomic_test_and_set'
1 This pattern emits code for '__builtin_atomic_test_and_set'.
1 Operand 0 is an output operand which is set to true if the previous
1 previous contents of the byte was "set", and false otherwise.
1 Operand 1 is the 'QImode' memory to be modified. Operand 2 is the
1 memory model to be used.
1
1 The specific value that defines "set" is implementation defined,
1 and is normally based on what is performed by the native atomic
1 test and set instruction.
1
1 'atomic_bit_test_and_setMODE'
1 'atomic_bit_test_and_complementMODE'
1 'atomic_bit_test_and_resetMODE'
1 These patterns emit code for an atomic bitwise operation on memory
1 with memory model semantics, and return the original value of the
1 specified bit. Operand 0 is an output operand which contains the
1 value of the specified bit from the memory location before the
1 operation was performed. Operand 1 is the memory on which the
1 atomic operation is performed. Operand 2 is the bit within the
1 operand, starting with least significant bit. Operand 3 is the
1 memory model to be used by the operation. Operand 4 is a flag - it
1 is 'const1_rtx' if operand 0 should contain the original value of
1 the specified bit in the least significant bit of the operand, and
1 'const0_rtx' if the bit should be in its original position in the
1 operand. 'atomic_bit_test_and_setMODE' atomically sets the
1 specified bit after remembering its original value,
1 'atomic_bit_test_and_complementMODE' inverts the specified bit and
1 'atomic_bit_test_and_resetMODE' clears the specified bit.
1
1 If these patterns are not defined, attempts will be made to use
1 'atomic_fetch_orMODE', 'atomic_fetch_xorMODE' or
1 'atomic_fetch_andMODE' instruction patterns, or their 'sync'
1 counterparts. If none of these are available a compare-and-swap
1 loop will be used.
1
1 'mem_thread_fence'
1 This pattern emits code required to implement a thread fence with
1 memory model semantics. Operand 0 is the memory model to be used.
1
1 For the '__ATOMIC_RELAXED' model no instructions need to be issued
1 and this expansion is not invoked.
1
1 The compiler always emits a compiler memory barrier regardless of
1 what expanding this pattern produced.
1
1 If this pattern is not defined, the compiler falls back to
1 expanding the 'memory_barrier' pattern, then to emitting
1 '__sync_synchronize' library call, and finally to just placing a
1 compiler memory barrier.
1
1 'get_thread_pointerMODE'
1 'set_thread_pointerMODE'
1 These patterns emit code that reads/sets the TLS thread pointer.
1 Currently, these are only needed if the target needs to support the
1 '__builtin_thread_pointer' and '__builtin_set_thread_pointer'
1 builtins.
1
1 The get/set patterns have a single output/input operand
1 respectively, with MODE intended to be 'Pmode'.
1
1 'stack_protect_set'
1 This pattern, if defined, moves a 'ptr_mode' value from the memory
1 in operand 1 to the memory in operand 0 without leaving the value
1 in a register afterward. This is to avoid leaking the value some
1 place that an attacker might use to rewrite the stack guard slot
1 after having clobbered it.
1
1 If this pattern is not defined, then a plain move pattern is
1 generated.
1
1 'stack_protect_test'
1 This pattern, if defined, compares a 'ptr_mode' value from the
1 memory in operand 1 with the memory in operand 0 without leaving
1 the value in a register afterward and branches to operand 2 if the
1 values were equal.
1
1 If this pattern is not defined, then a plain compare pattern and
1 conditional branch pattern is used.
1
1 'clear_cache'
1 This pattern, if defined, flushes the instruction cache for a
1 region of memory. The region is bounded to by the Pmode pointers
1 in operand 0 inclusive and operand 1 exclusive.
1
1 If this pattern is not defined, a call to the library function
1 '__clear_cache' is used.
1