gccint: Register Classes
1
1 18.8 Register Classes
1 =====================
1
1 On many machines, the numbered registers are not all equivalent. For
1 example, certain registers may not be allowed for indexed addressing;
1 certain registers may not be allowed in some instructions. These
1 machine restrictions are described to the compiler using "register
1 classes".
1
1 You define a number of register classes, giving each one a name and
1 saying which of the registers belong to it. Then you can specify
1 register classes that are allowed as operands to particular instruction
1 patterns.
1
1 In general, each register will belong to several classes. In fact, one
1 class must be named 'ALL_REGS' and contain all the registers. Another
1 class must be named 'NO_REGS' and contain no registers. Often the union
1 of two classes will be another class; however, this is not required.
1
1 One of the classes must be named 'GENERAL_REGS'. There is nothing
1 terribly special about the name, but the operand constraint letters 'r'
1 and 'g' specify this class. If 'GENERAL_REGS' is the same as
1 'ALL_REGS', just define it as a macro which expands to 'ALL_REGS'.
1
1 Order the classes so that if class X is contained in class Y then X has
1 a lower class number than Y.
1
1 The way classes other than 'GENERAL_REGS' are specified in operand
1 constraints is through machine-dependent operand constraint letters.
1 You can define such letters to correspond to various classes, then use
1 them in operand constraints.
1
1 You must define the narrowest register classes for allocatable
1 registers, so that each class either has no subclasses, or that for some
1 mode, the move cost between registers within the class is cheaper than
1 moving a register in the class to or from memory (⇒Costs).
1
1 You should define a class for the union of two classes whenever some
1 instruction allows both classes. For example, if an instruction allows
1 either a floating point (coprocessor) register or a general register for
1 a certain operand, you should define a class 'FLOAT_OR_GENERAL_REGS'
1 which includes both of them. Otherwise you will get suboptimal code, or
1 even internal compiler errors when reload cannot find a register in the
1 class computed via 'reg_class_subunion'.
1
1 You must also specify certain redundant information about the register
1 classes: for each class, which classes contain it and which ones are
1 contained in it; for each pair of classes, the largest class contained
1 in their union.
1
1 When a value occupying several consecutive registers is expected in a
1 certain class, all the registers used must belong to that class.
1 Therefore, register classes cannot be used to enforce a requirement for
1 a register pair to start with an even-numbered register. The way to
1 specify this requirement is with 'TARGET_HARD_REGNO_MODE_OK'.
1
1 Register classes used for input-operands of bitwise-and or shift
1 instructions have a special requirement: each such class must have, for
1 each fixed-point machine mode, a subclass whose registers can transfer
1 that mode to or from memory. For example, on some machines, the
1 operations for single-byte values ('QImode') are limited to certain
1 registers. When this is so, each register class that is used in a
1 bitwise-and or shift instruction must have a subclass consisting of
1 registers from which single-byte values can be loaded or stored. This
1 is so that 'PREFERRED_RELOAD_CLASS' can always have a possible value to
1 return.
1
1 -- Data type: enum reg_class
1 An enumerated type that must be defined with all the register class
1 names as enumerated values. 'NO_REGS' must be first. 'ALL_REGS'
1 must be the last register class, followed by one more enumerated
1 value, 'LIM_REG_CLASSES', which is not a register class but rather
1 tells how many classes there are.
1
1 Each register class has a number, which is the value of casting the
1 class name to type 'int'. The number serves as an index in many of
1 the tables described below.
1
1 -- Macro: N_REG_CLASSES
1 The number of distinct register classes, defined as follows:
1
1 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1
1 -- Macro: REG_CLASS_NAMES
1 An initializer containing the names of the register classes as C
1 string constants. These names are used in writing some of the
1 debugging dumps.
1
1 -- Macro: REG_CLASS_CONTENTS
1 An initializer containing the contents of the register classes, as
1 integers which are bit masks. The Nth integer specifies the
1 contents of class N. The way the integer MASK is interpreted is
1 that register R is in the class if 'MASK & (1 << R)' is 1.
1
1 When the machine has more than 32 registers, an integer does not
1 suffice. Then the integers are replaced by sub-initializers,
1 braced groupings containing several integers. Each sub-initializer
1 must be suitable as an initializer for the type 'HARD_REG_SET'
1 which is defined in 'hard-reg-set.h'. In this situation, the first
1 integer in each sub-initializer corresponds to registers 0 through
1 31, the second integer to registers 32 through 63, and so on.
1
1 -- Macro: REGNO_REG_CLASS (REGNO)
1 A C expression whose value is a register class containing hard
1 register REGNO. In general there is more than one such class;
1 choose a class which is "minimal", meaning that no smaller class
1 also contains the register.
1
1 -- Macro: BASE_REG_CLASS
1 A macro whose definition is the name of the class to which a valid
1 base register must belong. A base register is one used in an
1 address which is the register value plus a displacement.
1
1 -- Macro: MODE_BASE_REG_CLASS (MODE)
1 This is a variation of the 'BASE_REG_CLASS' macro which allows the
1 selection of a base register in a mode dependent manner. If MODE
1 is VOIDmode then it should return the same value as
1 'BASE_REG_CLASS'.
1
1 -- Macro: MODE_BASE_REG_REG_CLASS (MODE)
1 A C expression whose value is the register class to which a valid
1 base register must belong in order to be used in a base plus index
1 register address. You should define this macro if base plus index
1 addresses have different requirements than other base register
1 uses.
1
1 -- Macro: MODE_CODE_BASE_REG_CLASS (MODE, ADDRESS_SPACE, OUTER_CODE,
1 INDEX_CODE)
1 A C expression whose value is the register class to which a valid
1 base register for a memory reference in mode MODE to address space
1 ADDRESS_SPACE must belong. OUTER_CODE and INDEX_CODE define the
1 context in which the base register occurs. OUTER_CODE is the code
1 of the immediately enclosing expression ('MEM' for the top level of
1 an address, 'ADDRESS' for something that occurs in an
1 'address_operand'). INDEX_CODE is the code of the corresponding
1 index expression if OUTER_CODE is 'PLUS'; 'SCRATCH' otherwise.
1
1 -- Macro: INDEX_REG_CLASS
1 A macro whose definition is the name of the class to which a valid
1 index register must belong. An index register is one used in an
1 address where its value is either multiplied by a scale factor or
1 added to another register (as well as added to a displacement).
1
1 -- Macro: REGNO_OK_FOR_BASE_P (NUM)
1 A C expression which is nonzero if register number NUM is suitable
1 for use as a base register in operand addresses.
1
1 -- Macro: REGNO_MODE_OK_FOR_BASE_P (NUM, MODE)
1 A C expression that is just like 'REGNO_OK_FOR_BASE_P', except that
1 that expression may examine the mode of the memory reference in
1 MODE. You should define this macro if the mode of the memory
1 reference affects whether a register may be used as a base
1 register. If you define this macro, the compiler will use it
1 instead of 'REGNO_OK_FOR_BASE_P'. The mode may be 'VOIDmode' for
1 addresses that appear outside a 'MEM', i.e., as an
1 'address_operand'.
1
1 -- Macro: REGNO_MODE_OK_FOR_REG_BASE_P (NUM, MODE)
1 A C expression which is nonzero if register number NUM is suitable
1 for use as a base register in base plus index operand addresses,
1 accessing memory in mode MODE. It may be either a suitable hard
1 register or a pseudo register that has been allocated such a hard
1 register. You should define this macro if base plus index
1 addresses have different requirements than other base register
1 uses.
1
1 Use of this macro is deprecated; please use the more general
1 'REGNO_MODE_CODE_OK_FOR_BASE_P'.
1
1 -- Macro: REGNO_MODE_CODE_OK_FOR_BASE_P (NUM, MODE, ADDRESS_SPACE,
1 OUTER_CODE, INDEX_CODE)
1 A C expression which is nonzero if register number NUM is suitable
1 for use as a base register in operand addresses, accessing memory
1 in mode MODE in address space ADDRESS_SPACE. This is similar to
1 'REGNO_MODE_OK_FOR_BASE_P', except that that expression may examine
1 the context in which the register appears in the memory reference.
1 OUTER_CODE is the code of the immediately enclosing expression
1 ('MEM' if at the top level of the address, 'ADDRESS' for something
1 that occurs in an 'address_operand'). INDEX_CODE is the code of
1 the corresponding index expression if OUTER_CODE is 'PLUS';
1 'SCRATCH' otherwise. The mode may be 'VOIDmode' for addresses that
1 appear outside a 'MEM', i.e., as an 'address_operand'.
1
1 -- Macro: REGNO_OK_FOR_INDEX_P (NUM)
1 A C expression which is nonzero if register number NUM is suitable
1 for use as an index register in operand addresses. It may be
1 either a suitable hard register or a pseudo register that has been
1 allocated such a hard register.
1
1 The difference between an index register and a base register is
1 that the index register may be scaled. If an address involves the
1 sum of two registers, neither one of them scaled, then either one
1 may be labeled the "base" and the other the "index"; but whichever
1 labeling is used must fit the machine's constraints of which
1 registers may serve in each capacity. The compiler will try both
1 labelings, looking for one that is valid, and will reload one or
1 both registers only if neither labeling works.
1
1 -- Target Hook: reg_class_t TARGET_PREFERRED_RENAME_CLASS (reg_class_t
1 RCLASS)
1 A target hook that places additional preference on the register
1 class to use when it is necessary to rename a register in class
1 RCLASS to another class, or perhaps NO_REGS, if no preferred
1 register class is found or hook 'preferred_rename_class' is not
1 implemented. Sometimes returning a more restrictive class makes
1 better code. For example, on ARM, thumb-2 instructions using
1 'LO_REGS' may be smaller than instructions using 'GENERIC_REGS'.
1 By returning 'LO_REGS' from 'preferred_rename_class', code size can
1 be reduced.
1
1 -- Target Hook: reg_class_t TARGET_PREFERRED_RELOAD_CLASS (rtx X,
1 reg_class_t RCLASS)
1 A target hook that places additional restrictions on the register
1 class to use when it is necessary to copy value X into a register
1 in class RCLASS. The value is a register class; perhaps RCLASS, or
1 perhaps another, smaller class.
1
1 The default version of this hook always returns value of 'rclass'
1 argument.
1
1 Sometimes returning a more restrictive class makes better code.
1 For example, on the 68000, when X is an integer constant that is in
1 range for a 'moveq' instruction, the value of this macro is always
1 'DATA_REGS' as long as RCLASS includes the data registers.
1 Requiring a data register guarantees that a 'moveq' will be used.
1
1 One case where 'TARGET_PREFERRED_RELOAD_CLASS' must not return
1 RCLASS is if X is a legitimate constant which cannot be loaded into
1 some register class. By returning 'NO_REGS' you can force X into a
1 memory location. For example, rs6000 can load immediate values
1 into general-purpose registers, but does not have an instruction
1 for loading an immediate value into a floating-point register, so
1 'TARGET_PREFERRED_RELOAD_CLASS' returns 'NO_REGS' when X is a
1 floating-point constant. If the constant can't be loaded into any
1 kind of register, code generation will be better if
1 'TARGET_LEGITIMATE_CONSTANT_P' makes the constant illegitimate
1 instead of using 'TARGET_PREFERRED_RELOAD_CLASS'.
1
1 If an insn has pseudos in it after register allocation, reload will
1 go through the alternatives and call repeatedly
1 'TARGET_PREFERRED_RELOAD_CLASS' to find the best one. Returning
1 'NO_REGS', in this case, makes reload add a '!' in front of the
1 constraint: the x86 back-end uses this feature to discourage usage
1 of 387 registers when math is done in the SSE registers (and vice
1 versa).
1
1 -- Macro: PREFERRED_RELOAD_CLASS (X, CLASS)
1 A C expression that places additional restrictions on the register
1 class to use when it is necessary to copy value X into a register
1 in class CLASS. The value is a register class; perhaps CLASS, or
1 perhaps another, smaller class. On many machines, the following
1 definition is safe:
1
1 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
1
1 Sometimes returning a more restrictive class makes better code.
1 For example, on the 68000, when X is an integer constant that is in
1 range for a 'moveq' instruction, the value of this macro is always
1 'DATA_REGS' as long as CLASS includes the data registers.
1 Requiring a data register guarantees that a 'moveq' will be used.
1
1 One case where 'PREFERRED_RELOAD_CLASS' must not return CLASS is if
1 X is a legitimate constant which cannot be loaded into some
1 register class. By returning 'NO_REGS' you can force X into a
1 memory location. For example, rs6000 can load immediate values
1 into general-purpose registers, but does not have an instruction
1 for loading an immediate value into a floating-point register, so
1 'PREFERRED_RELOAD_CLASS' returns 'NO_REGS' when X is a
1 floating-point constant. If the constant cannot be loaded into any
1 kind of register, code generation will be better if
1 'TARGET_LEGITIMATE_CONSTANT_P' makes the constant illegitimate
1 instead of using 'TARGET_PREFERRED_RELOAD_CLASS'.
1
1 If an insn has pseudos in it after register allocation, reload will
1 go through the alternatives and call repeatedly
1 'PREFERRED_RELOAD_CLASS' to find the best one. Returning
1 'NO_REGS', in this case, makes reload add a '!' in front of the
1 constraint: the x86 back-end uses this feature to discourage usage
1 of 387 registers when math is done in the SSE registers (and vice
1 versa).
1
1 -- Target Hook: reg_class_t TARGET_PREFERRED_OUTPUT_RELOAD_CLASS (rtx
1 X, reg_class_t RCLASS)
1 Like 'TARGET_PREFERRED_RELOAD_CLASS', but for output reloads
1 instead of input reloads.
1
1 The default version of this hook always returns value of 'rclass'
1 argument.
1
1 You can also use 'TARGET_PREFERRED_OUTPUT_RELOAD_CLASS' to
1 discourage reload from using some alternatives, like
1 'TARGET_PREFERRED_RELOAD_CLASS'.
1
1 -- Macro: LIMIT_RELOAD_CLASS (MODE, CLASS)
1 A C expression that places additional restrictions on the register
1 class to use when it is necessary to be able to hold a value of
1 mode MODE in a reload register for which class CLASS would
1 ordinarily be used.
1
1 Unlike 'PREFERRED_RELOAD_CLASS', this macro should be used when
1 there are certain modes that simply cannot go in certain reload
1 classes.
1
1 The value is a register class; perhaps CLASS, or perhaps another,
1 smaller class.
1
1 Don't define this macro unless the target machine has limitations
1 which require the macro to do something nontrivial.
1
1 -- Target Hook: reg_class_t TARGET_SECONDARY_RELOAD (bool IN_P, rtx X,
1 reg_class_t RELOAD_CLASS, machine_mode RELOAD_MODE,
1 secondary_reload_info *SRI)
1 Many machines have some registers that cannot be copied directly to
1 or from memory or even from other types of registers. An example
1 is the 'MQ' register, which on most machines, can only be copied to
1 or from general registers, but not memory. Below, we shall be
1 using the term 'intermediate register' when a move operation cannot
1 be performed directly, but has to be done by copying the source
1 into the intermediate register first, and then copying the
1 intermediate register to the destination. An intermediate register
1 always has the same mode as source and destination. Since it holds
1 the actual value being copied, reload might apply optimizations to
1 re-use an intermediate register and eliding the copy from the
1 source when it can determine that the intermediate register still
1 holds the required value.
1
1 Another kind of secondary reload is required on some machines which
1 allow copying all registers to and from memory, but require a
1 scratch register for stores to some memory locations (e.g., those
1 with symbolic address on the RT, and those with certain symbolic
1 address on the SPARC when compiling PIC). Scratch registers need
1 not have the same mode as the value being copied, and usually hold
1 a different value than that being copied. Special patterns in the
1 md file are needed to describe how the copy is performed with the
1 help of the scratch register; these patterns also describe the
1 number, register class(es) and mode(s) of the scratch register(s).
1
1 In some cases, both an intermediate and a scratch register are
1 required.
1
1 For input reloads, this target hook is called with nonzero IN_P,
1 and X is an rtx that needs to be copied to a register of class
1 RELOAD_CLASS in RELOAD_MODE. For output reloads, this target hook
1 is called with zero IN_P, and a register of class RELOAD_CLASS
1 needs to be copied to rtx X in RELOAD_MODE.
1
1 If copying a register of RELOAD_CLASS from/to X requires an
1 intermediate register, the hook 'secondary_reload' should return
1 the register class required for this intermediate register. If no
1 intermediate register is required, it should return NO_REGS. If
1 more than one intermediate register is required, describe the one
1 that is closest in the copy chain to the reload register.
1
1 If scratch registers are needed, you also have to describe how to
1 perform the copy from/to the reload register to/from this closest
1 intermediate register. Or if no intermediate register is required,
1 but still a scratch register is needed, describe the copy from/to
1 the reload register to/from the reload operand X.
1
1 You do this by setting 'sri->icode' to the instruction code of a
1 pattern in the md file which performs the move. Operands 0 and 1
1 are the output and input of this copy, respectively. Operands from
1 operand 2 onward are for scratch operands. These scratch operands
1 must have a mode, and a single-register-class output constraint.
1
1 When an intermediate register is used, the 'secondary_reload' hook
1 will be called again to determine how to copy the intermediate
1 register to/from the reload operand X, so your hook must also have
1 code to handle the register class of the intermediate operand.
1
1 X might be a pseudo-register or a 'subreg' of a pseudo-register,
1 which could either be in a hard register or in memory. Use
1 'true_regnum' to find out; it will return -1 if the pseudo is in
1 memory and the hard register number if it is in a register.
1
1 Scratch operands in memory (constraint '"=m"' / '"=&m"') are
1 currently not supported. For the time being, you will have to
1 continue to use 'TARGET_SECONDARY_MEMORY_NEEDED' for that purpose.
1
1 'copy_cost' also uses this target hook to find out how values are
1 copied. If you want it to include some extra cost for the need to
1 allocate (a) scratch register(s), set 'sri->extra_cost' to the
1 additional cost. Or if two dependent moves are supposed to have a
1 lower cost than the sum of the individual moves due to expected
1 fortuitous scheduling and/or special forwarding logic, you can set
1 'sri->extra_cost' to a negative amount.
1
1 -- Macro: SECONDARY_RELOAD_CLASS (CLASS, MODE, X)
1 -- Macro: SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)
1 -- Macro: SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)
1 These macros are obsolete, new ports should use the target hook
1 'TARGET_SECONDARY_RELOAD' instead.
1
1 These are obsolete macros, replaced by the
1 'TARGET_SECONDARY_RELOAD' target hook. Older ports still define
1 these macros to indicate to the reload phase that it may need to
1 allocate at least one register for a reload in addition to the
1 register to contain the data. Specifically, if copying X to a
1 register CLASS in MODE requires an intermediate register, you were
1 supposed to define 'SECONDARY_INPUT_RELOAD_CLASS' to return the
1 largest register class all of whose registers can be used as
1 intermediate registers or scratch registers.
1
1 If copying a register CLASS in MODE to X requires an intermediate
1 or scratch register, 'SECONDARY_OUTPUT_RELOAD_CLASS' was supposed
1 to be defined be defined to return the largest register class
1 required. If the requirements for input and output reloads were
1 the same, the macro 'SECONDARY_RELOAD_CLASS' should have been used
1 instead of defining both macros identically.
1
1 The values returned by these macros are often 'GENERAL_REGS'.
1 Return 'NO_REGS' if no spare register is needed; i.e., if X can be
1 directly copied to or from a register of CLASS in MODE without
1 requiring a scratch register. Do not define this macro if it would
1 always return 'NO_REGS'.
1
1 If a scratch register is required (either with or without an
1 intermediate register), you were supposed to define patterns for
1 'reload_inM' or 'reload_outM', as required (⇒Standard Names.
1 These patterns, which were normally implemented with a
1 'define_expand', should be similar to the 'movM' patterns, except
1 that operand 2 is the scratch register.
1
1 These patterns need constraints for the reload register and scratch
1 register that contain a single register class. If the original
1 reload register (whose class is CLASS) can meet the constraint
1 given in the pattern, the value returned by these macros is used
1 for the class of the scratch register. Otherwise, two additional
1 reload registers are required. Their classes are obtained from the
1 constraints in the insn pattern.
1
1 X might be a pseudo-register or a 'subreg' of a pseudo-register,
1 which could either be in a hard register or in memory. Use
1 'true_regnum' to find out; it will return -1 if the pseudo is in
1 memory and the hard register number if it is in a register.
1
1 These macros should not be used in the case where a particular
1 class of registers can only be copied to memory and not to another
1 class of registers. In that case, secondary reload registers are
1 not needed and would not be helpful. Instead, a stack location
1 must be used to perform the copy and the 'movM' pattern should use
1 memory as an intermediate storage. This case often occurs between
1 floating-point and general registers.
1
1 -- Target Hook: bool TARGET_SECONDARY_MEMORY_NEEDED (machine_mode MODE,
1 reg_class_t CLASS1, reg_class_t CLASS2)
1 Certain machines have the property that some registers cannot be
1 copied to some other registers without using memory. Define this
1 hook on those machines to return true if objects of mode M in
1 registers of CLASS1 can only be copied to registers of class CLASS2
1 by storing a register of CLASS1 into memory and loading that memory
1 location into a register of CLASS2. The default definition returns
1 false for all inputs.
1
1 -- Macro: SECONDARY_MEMORY_NEEDED_RTX (MODE)
1 Normally when 'TARGET_SECONDARY_MEMORY_NEEDED' is defined, the
1 compiler allocates a stack slot for a memory location needed for
1 register copies. If this macro is defined, the compiler instead
1 uses the memory location defined by this macro.
1
1 Do not define this macro if you do not define
1 'TARGET_SECONDARY_MEMORY_NEEDED'.
1
1 -- Target Hook: machine_mode TARGET_SECONDARY_MEMORY_NEEDED_MODE
1 (machine_mode MODE)
1 If 'TARGET_SECONDARY_MEMORY_NEEDED' tells the compiler to use
1 memory when moving between two particular registers of mode MODE,
1 this hook specifies the mode that the memory should have.
1
1 The default depends on 'TARGET_LRA_P'. Without LRA, the default is
1 to use a word-sized mode for integral modes that are smaller than a
1 a word. This is right thing to do on most machines because it
1 ensures that all bits of the register are copied and prevents
1 accesses to the registers in a narrower mode, which some machines
1 prohibit for floating-point registers.
1
1 However, this default behavior is not correct on some machines,
1 such as the DEC Alpha, that store short integers in floating-point
1 registers differently than in integer registers. On those
1 machines, the default widening will not work correctly and you must
1 define this hook to suppress that widening in some cases. See the
1 file 'alpha.c' for details.
1
1 With LRA, the default is to use MODE unmodified.
1
1 -- Target Hook: void TARGET_SELECT_EARLY_REMAT_MODES (sbitmap MODES)
1 On some targets, certain modes cannot be held in registers around a
1 standard ABI call and are relatively expensive to spill to the
1 stack. The early rematerialization pass can help in such cases by
1 aggressively recomputing values after calls, so that they don't
1 need to be spilled.
1
1 This hook returns the set of such modes by setting the associated
1 bits in MODES. The default implementation selects no modes, which
1 has the effect of disabling the early rematerialization pass.
1
1 -- Target Hook: bool TARGET_CLASS_LIKELY_SPILLED_P (reg_class_t RCLASS)
1 A target hook which returns 'true' if pseudos that have been
1 assigned to registers of class RCLASS would likely be spilled
1 because registers of RCLASS are needed for spill registers.
1
1 The default version of this target hook returns 'true' if RCLASS
1 has exactly one register and 'false' otherwise. On most machines,
1 this default should be used. For generally register-starved
1 machines, such as i386, or machines with right register
1 constraints, such as SH, this hook can be used to avoid excessive
1 spilling.
1
1 This hook is also used by some of the global intra-procedural code
1 transformations to throtle code motion, to avoid increasing
1 register pressure.
1
1 -- Target Hook: unsigned char TARGET_CLASS_MAX_NREGS (reg_class_t
1 RCLASS, machine_mode MODE)
1 A target hook returns the maximum number of consecutive registers
1 of class RCLASS needed to hold a value of mode MODE.
1
1 This is closely related to the macro 'TARGET_HARD_REGNO_NREGS'. In
1 fact, the value returned by 'TARGET_CLASS_MAX_NREGS (RCLASS, MODE)'
1 target hook should be the maximum value of 'TARGET_HARD_REGNO_NREGS
1 (REGNO, MODE)' for all REGNO values in the class RCLASS.
1
1 This target hook helps control the handling of multiple-word values
1 in the reload pass.
1
1 The default version of this target hook returns the size of MODE in
1 words.
1
1 -- Macro: CLASS_MAX_NREGS (CLASS, MODE)
1 A C expression for the maximum number of consecutive registers of
1 class CLASS needed to hold a value of mode MODE.
1
1 This is closely related to the macro 'TARGET_HARD_REGNO_NREGS'. In
1 fact, the value of the macro 'CLASS_MAX_NREGS (CLASS, MODE)' should
1 be the maximum value of 'TARGET_HARD_REGNO_NREGS (REGNO, MODE)' for
1 all REGNO values in the class CLASS.
1
1 This macro helps control the handling of multiple-word values in
1 the reload pass.
1
1 -- Target Hook: bool TARGET_CAN_CHANGE_MODE_CLASS (machine_mode FROM,
1 machine_mode TO, reg_class_t RCLASS)
1 This hook returns true if it is possible to bitcast values held in
1 registers of class RCLASS from mode FROM to mode TO and if doing so
1 preserves the low-order bits that are common to both modes. The
1 result is only meaningful if RCLASS has registers that can hold
1 both 'from' and 'to'. The default implementation returns true.
1
1 As an example of when such bitcasting is invalid, loading 32-bit
1 integer or floating-point objects into floating-point registers on
1 Alpha extends them to 64 bits. Therefore loading a 64-bit object
1 and then storing it as a 32-bit object does not store the low-order
1 32 bits, as would be the case for a normal register. Therefore,
1 'alpha.h' defines 'TARGET_CAN_CHANGE_MODE_CLASS' to return:
1
1 (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)
1 || !reg_classes_intersect_p (FLOAT_REGS, rclass))
1
1 Even if storing from a register in mode TO would be valid, if both
1 FROM and 'raw_reg_mode' for RCLASS are wider than 'word_mode', then
1 we must prevent TO narrowing the mode. This happens when the
1 middle-end assumes that it can load or store pieces of an N-word
1 pseudo, and that the pseudo will eventually be allocated to N
1 'word_mode' hard registers. Failure to prevent this kind of mode
1 change will result in the entire 'raw_reg_mode' being modified
1 instead of the partial value that the middle-end intended.
1
1 -- Target Hook: reg_class_t TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
1 (int, REG_CLASS_T, REG_CLASS_T)
1 A target hook which can change allocno class for given pseudo from
1 allocno and best class calculated by IRA.
1
1 The default version of this target hook always returns given class.
1
1 -- Target Hook: bool TARGET_LRA_P (void)
1 A target hook which returns true if we use LRA instead of reload
1 pass. The default version of this target hook returns true. New
1 ports should use LRA, and existing ports are encouraged to convert.
1
1 -- Target Hook: int TARGET_REGISTER_PRIORITY (int)
1 A target hook which returns the register priority number to which
1 the register HARD_REGNO belongs to. The bigger the number, the
1 more preferable the hard register usage (when all other conditions
1 are the same). This hook can be used to prefer some hard register
1 over others in LRA. For example, some x86-64 register usage needs
1 additional prefix which makes instructions longer. The hook can
1 return lower priority number for such registers make them less
1 favorable and as result making the generated code smaller. The
1 default version of this target hook returns always zero.
1
1 -- Target Hook: bool TARGET_REGISTER_USAGE_LEVELING_P (void)
1 A target hook which returns true if we need register usage
1 leveling. That means if a few hard registers are equally good for
1 the assignment, we choose the least used hard register. The
1 register usage leveling may be profitable for some targets. Don't
1 use the usage leveling for targets with conditional execution or
1 targets with big register files as it hurts if-conversion and
1 cross-jumping optimizations. The default version of this target
1 hook returns always false.
1
1 -- Target Hook: bool TARGET_DIFFERENT_ADDR_DISPLACEMENT_P (void)
1 A target hook which returns true if an address with the same
1 structure can have different maximal legitimate displacement. For
1 example, the displacement can depend on memory mode or on operand
1 combinations in the insn. The default version of this target hook
1 returns always false.
1
1 -- Target Hook: bool TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P (rtx SUBST)
1 A target hook which returns 'true' if SUBST can't substitute safely
1 pseudos with equivalent memory values during register allocation.
1 The default version of this target hook returns 'false'. On most
1 machines, this default should be used. For generally machines with
1 non orthogonal register usage for addressing, such as SH, this hook
1 can be used to avoid excessive spilling.
1
1 -- Target Hook: bool TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT (rtx
1 *OFFSET1, rtx *OFFSET2, poly_int64 ORIG_OFFSET, machine_mode
1 MODE)
1 This hook tries to split address offset ORIG_OFFSET into two parts:
1 one that should be added to the base address to create a local
1 anchor point, and an additional offset that can be applied to the
1 anchor to address a value of mode MODE. The idea is that the local
1 anchor could be shared by other accesses to nearby locations.
1
1 The hook returns true if it succeeds, storing the offset of the
1 anchor from the base in OFFSET1 and the offset of the final address
1 from the anchor in OFFSET2. The default implementation returns
1 false.
1
1 -- Target Hook: reg_class_t TARGET_SPILL_CLASS (reg_class_t,
1 MACHINE_MODE)
1 This hook defines a class of registers which could be used for
1 spilling pseudos of the given mode and class, or 'NO_REGS' if only
1 memory should be used. Not defining this hook is equivalent to
1 returning 'NO_REGS' for all inputs.
1
1 -- Target Hook: bool TARGET_ADDITIONAL_ALLOCNO_CLASS_P (reg_class_t)
1 This hook should return 'true' if given class of registers should
1 be an allocno class in any way. Usually RA uses only one register
1 class from all classes containing the same register set. In some
1 complicated cases, you need to have two or more such classes as
1 allocno ones for RA correct work. Not defining this hook is
1 equivalent to returning 'false' for all inputs.
1
1 -- Target Hook: scalar_int_mode TARGET_CSTORE_MODE (enum insn_code
1 ICODE)
1 This hook defines the machine mode to use for the boolean result of
1 conditional store patterns. The ICODE argument is the instruction
1 code for the cstore being performed. Not definiting this hook is
1 the same as accepting the mode encoded into operand 0 of the cstore
1 expander patterns.
1
1 -- Target Hook: int TARGET_COMPUTE_PRESSURE_CLASSES (enum reg_class
1 *PRESSURE_CLASSES)
1 A target hook which lets a backend compute the set of pressure
1 classes to be used by those optimization passes which take register
1 pressure into account, as opposed to letting IRA compute them. It
1 returns the number of register classes stored in the array
1 PRESSURE_CLASSES.
1