gcc: ARC Options
1
1 3.18.3 ARC Options
1 ------------------
1
1 The following options control the architecture variant for which code is
1 being compiled:
1
1 '-mbarrel-shifter'
1 Generate instructions supported by barrel shifter. This is the
1 default unless '-mcpu=ARC601' or '-mcpu=ARCEM' is in effect.
1
1 '-mjli-always'
1 Force to call a function using jli_s instruction. This option is
1 valid only for ARCv2 architecture.
1
1 '-mcpu=CPU'
1 Set architecture type, register usage, and instruction scheduling
1 parameters for CPU. There are also shortcut alias options
1 available for backward compatibility and convenience. Supported
1 values for CPU are
1
1 'arc600'
1 Compile for ARC600. Aliases: '-mA6', '-mARC600'.
1
1 'arc601'
1 Compile for ARC601. Alias: '-mARC601'.
1
1 'arc700'
1 Compile for ARC700. Aliases: '-mA7', '-mARC700'. This is the
1 default when configured with '--with-cpu=arc700'.
1
1 'arcem'
1 Compile for ARC EM.
1
1 'archs'
1 Compile for ARC HS.
1
1 'em'
1 Compile for ARC EM CPU with no hardware extensions.
1
1 'em4'
1 Compile for ARC EM4 CPU.
1
1 'em4_dmips'
1 Compile for ARC EM4 DMIPS CPU.
1
1 'em4_fpus'
1 Compile for ARC EM4 DMIPS CPU with the single-precision
1 floating-point extension.
1
1 'em4_fpuda'
1 Compile for ARC EM4 DMIPS CPU with single-precision
1 floating-point and double assist instructions.
1
1 'hs'
1 Compile for ARC HS CPU with no hardware extensions except the
1 atomic instructions.
1
1 'hs34'
1 Compile for ARC HS34 CPU.
1
1 'hs38'
1 Compile for ARC HS38 CPU.
1
1 'hs38_linux'
1 Compile for ARC HS38 CPU with all hardware extensions on.
1
1 'arc600_norm'
1 Compile for ARC 600 CPU with 'norm' instructions enabled.
1
1 'arc600_mul32x16'
1 Compile for ARC 600 CPU with 'norm' and 32x16-bit multiply
1 instructions enabled.
1
1 'arc600_mul64'
1 Compile for ARC 600 CPU with 'norm' and 'mul64'-family
1 instructions enabled.
1
1 'arc601_norm'
1 Compile for ARC 601 CPU with 'norm' instructions enabled.
1
1 'arc601_mul32x16'
1 Compile for ARC 601 CPU with 'norm' and 32x16-bit multiply
1 instructions enabled.
1
1 'arc601_mul64'
1 Compile for ARC 601 CPU with 'norm' and 'mul64'-family
1 instructions enabled.
1
1 'nps400'
1 Compile for ARC 700 on NPS400 chip.
1
1 'em_mini'
1 Compile for ARC EM minimalist configuration featuring reduced
1 register set.
1
1 '-mdpfp'
1 '-mdpfp-compact'
1 Generate double-precision FPX instructions, tuned for the compact
1 implementation.
1
1 '-mdpfp-fast'
1 Generate double-precision FPX instructions, tuned for the fast
1 implementation.
1
1 '-mno-dpfp-lrsr'
1 Disable 'lr' and 'sr' instructions from using FPX extension aux
1 registers.
1
1 '-mea'
1 Generate extended arithmetic instructions. Currently only 'divaw',
1 'adds', 'subs', and 'sat16' are supported. This is always enabled
1 for '-mcpu=ARC700'.
1
1 '-mno-mpy'
1 Do not generate 'mpy'-family instructions for ARC700. This option
1 is deprecated.
1
1 '-mmul32x16'
1 Generate 32x16-bit multiply and multiply-accumulate instructions.
1
1 '-mmul64'
1 Generate 'mul64' and 'mulu64' instructions. Only valid for
1 '-mcpu=ARC600'.
1
1 '-mnorm'
1 Generate 'norm' instructions. This is the default if
1 '-mcpu=ARC700' is in effect.
1
1 '-mspfp'
1 '-mspfp-compact'
1 Generate single-precision FPX instructions, tuned for the compact
1 implementation.
1
1 '-mspfp-fast'
1 Generate single-precision FPX instructions, tuned for the fast
1 implementation.
1
1 '-msimd'
1 Enable generation of ARC SIMD instructions via target-specific
1 builtins. Only valid for '-mcpu=ARC700'.
1
1 '-msoft-float'
1 This option ignored; it is provided for compatibility purposes
1 only. Software floating-point code is emitted by default, and this
1 default can overridden by FPX options; '-mspfp', '-mspfp-compact',
1 or '-mspfp-fast' for single precision, and '-mdpfp',
1 '-mdpfp-compact', or '-mdpfp-fast' for double precision.
1
1 '-mswap'
1 Generate 'swap' instructions.
1
1 '-matomic'
1 This enables use of the locked load/store conditional extension to
1 implement atomic memory built-in functions. Not available for ARC
1 6xx or ARC EM cores.
1
1 '-mdiv-rem'
1 Enable 'div' and 'rem' instructions for ARCv2 cores.
1
1 '-mcode-density'
1 Enable code density instructions for ARC EM. This option is on by
1 default for ARC HS.
1
1 '-mll64'
1 Enable double load/store operations for ARC HS cores.
1
1 '-mtp-regno=REGNO'
1 Specify thread pointer register number.
1
1 '-mmpy-option=MULTO'
1 Compile ARCv2 code with a multiplier design option. You can
1 specify the option using either a string or numeric value for
1 MULTO. 'wlh1' is the default value. The recognized values are:
1
1 '0'
1 'none'
1 No multiplier available.
1
1 '1'
1 'w'
1 16x16 multiplier, fully pipelined. The following instructions
1 are enabled: 'mpyw' and 'mpyuw'.
1
1 '2'
1 'wlh1'
1 32x32 multiplier, fully pipelined (1 stage). The following
1 instructions are additionally enabled: 'mpy', 'mpyu', 'mpym',
1 'mpymu', and 'mpy_s'.
1
1 '3'
1 'wlh2'
1 32x32 multiplier, fully pipelined (2 stages). The following
1 instructions are additionally enabled: 'mpy', 'mpyu', 'mpym',
1 'mpymu', and 'mpy_s'.
1
1 '4'
1 'wlh3'
1 Two 16x16 multipliers, blocking, sequential. The following
1 instructions are additionally enabled: 'mpy', 'mpyu', 'mpym',
1 'mpymu', and 'mpy_s'.
1
1 '5'
1 'wlh4'
1 One 16x16 multiplier, blocking, sequential. The following
1 instructions are additionally enabled: 'mpy', 'mpyu', 'mpym',
1 'mpymu', and 'mpy_s'.
1
1 '6'
1 'wlh5'
1 One 32x4 multiplier, blocking, sequential. The following
1 instructions are additionally enabled: 'mpy', 'mpyu', 'mpym',
1 'mpymu', and 'mpy_s'.
1
1 '7'
1 'plus_dmpy'
1 ARC HS SIMD support.
1
1 '8'
1 'plus_macd'
1 ARC HS SIMD support.
1
1 '9'
1 'plus_qmacw'
1 ARC HS SIMD support.
1
1 This option is only available for ARCv2 cores.
1
1 '-mfpu=FPU'
1 Enables support for specific floating-point hardware extensions for
1 ARCv2 cores. Supported values for FPU are:
1
1 'fpus'
1 Enables support for single-precision floating-point hardware
1 extensions.
1
1 'fpud'
1 Enables support for double-precision floating-point hardware
1 extensions. The single-precision floating-point extension is
1 also enabled. Not available for ARC EM.
1
1 'fpuda'
1 Enables support for double-precision floating-point hardware
1 extensions using double-precision assist instructions. The
1 single-precision floating-point extension is also enabled.
1 This option is only available for ARC EM.
1
1 'fpuda_div'
1 Enables support for double-precision floating-point hardware
1 extensions using double-precision assist instructions. The
1 single-precision floating-point, square-root, and divide
1 extensions are also enabled. This option is only available
1 for ARC EM.
1
1 'fpuda_fma'
1 Enables support for double-precision floating-point hardware
1 extensions using double-precision assist instructions. The
1 single-precision floating-point and fused multiply and add
1 hardware extensions are also enabled. This option is only
1 available for ARC EM.
1
1 'fpuda_all'
1 Enables support for double-precision floating-point hardware
1 extensions using double-precision assist instructions. All
1 single-precision floating-point hardware extensions are also
1 enabled. This option is only available for ARC EM.
1
1 'fpus_div'
1 Enables support for single-precision floating-point,
1 square-root and divide hardware extensions.
1
1 'fpud_div'
1 Enables support for double-precision floating-point,
1 square-root and divide hardware extensions. This option
1 includes option 'fpus_div'. Not available for ARC EM.
1
1 'fpus_fma'
1 Enables support for single-precision floating-point and fused
1 multiply and add hardware extensions.
1
1 'fpud_fma'
1 Enables support for double-precision floating-point and fused
1 multiply and add hardware extensions. This option includes
1 option 'fpus_fma'. Not available for ARC EM.
1
1 'fpus_all'
1 Enables support for all single-precision floating-point
1 hardware extensions.
1
1 'fpud_all'
1 Enables support for all single- and double-precision
1 floating-point hardware extensions. Not available for ARC EM.
1
1 '-mirq-ctrl-saved=REGISTER-RANGE, BLINK, LP_COUNT'
1 Specifies general-purposes registers that the processor
1 automatically saves/restores on interrupt entry and exit.
1 REGISTER-RANGE is specified as two registers separated by a dash.
1 The register range always starts with 'r0', the upper limit is 'fp'
1 register. BLINK and LP_COUNT are optional. This option is only
1 valid for ARC EM and ARC HS cores.
1
1 '-mrgf-banked-regs=NUMBER'
1 Specifies the number of registers replicated in second register
1 bank on entry to fast interrupt. Fast interrupts are interrupts
1 with the highest priority level P0. These interrupts save only PC
1 and STATUS32 registers to avoid memory transactions during
1 interrupt entry and exit sequences. Use this option when you are
1 using fast interrupts in an ARC V2 family processor. Permitted
1 values are 4, 8, 16, and 32.
1
1 '-mlpc-width=WIDTH'
1 Specify the width of the 'lp_count' register. Valid values for
1 WIDTH are 8, 16, 20, 24, 28 and 32 bits. The default width is
1 fixed to 32 bits. If the width is less than 32, the compiler does
1 not attempt to transform loops in your program to use the
1 zero-delay loop mechanism unless it is known that the 'lp_count'
1 register can hold the required loop-counter value. Depending on
1 the width specified, the compiler and run-time library might
1 continue to use the loop mechanism for various needs. This option
1 defines macro '__ARC_LPC_WIDTH__' with the value of WIDTH.
1
1 '-mrf16'
1 This option instructs the compiler to generate code for a 16-entry
1 register file. This option defines the '__ARC_RF16__' preprocessor
1 macro.
1
1 The following options are passed through to the assembler, and also
1 define preprocessor macro symbols.
1
1 '-mdsp-packa'
1 Passed down to the assembler to enable the DSP Pack A extensions.
1 Also sets the preprocessor symbol '__Xdsp_packa'. This option is
1 deprecated.
1
1 '-mdvbf'
1 Passed down to the assembler to enable the dual Viterbi butterfly
1 extension. Also sets the preprocessor symbol '__Xdvbf'. This
1 option is deprecated.
1
1 '-mlock'
1 Passed down to the assembler to enable the locked load/store
1 conditional extension. Also sets the preprocessor symbol
1 '__Xlock'.
1
1 '-mmac-d16'
1 Passed down to the assembler. Also sets the preprocessor symbol
1 '__Xxmac_d16'. This option is deprecated.
1
1 '-mmac-24'
1 Passed down to the assembler. Also sets the preprocessor symbol
1 '__Xxmac_24'. This option is deprecated.
1
1 '-mrtsc'
1 Passed down to the assembler to enable the 64-bit time-stamp
1 counter extension instruction. Also sets the preprocessor symbol
1 '__Xrtsc'. This option is deprecated.
1
1 '-mswape'
1 Passed down to the assembler to enable the swap byte ordering
1 extension instruction. Also sets the preprocessor symbol
1 '__Xswape'.
1
1 '-mtelephony'
1 Passed down to the assembler to enable dual- and single-operand
1 instructions for telephony. Also sets the preprocessor symbol
1 '__Xtelephony'. This option is deprecated.
1
1 '-mxy'
1 Passed down to the assembler to enable the XY memory extension.
1 Also sets the preprocessor symbol '__Xxy'.
1
1 The following options control how the assembly code is annotated:
1
1 '-misize'
1 Annotate assembler instructions with estimated addresses.
1
1 '-mannotate-align'
1 Explain what alignment considerations lead to the decision to make
1 an instruction short or long.
1
1 The following options are passed through to the linker:
1
1 '-marclinux'
1 Passed through to the linker, to specify use of the 'arclinux'
1 emulation. This option is enabled by default in tool chains built
1 for 'arc-linux-uclibc' and 'arceb-linux-uclibc' targets when
1 profiling is not requested.
1
1 '-marclinux_prof'
1 Passed through to the linker, to specify use of the 'arclinux_prof'
1 emulation. This option is enabled by default in tool chains built
1 for 'arc-linux-uclibc' and 'arceb-linux-uclibc' targets when
1 profiling is requested.
1
1 The following options control the semantics of generated code:
1
1 '-mlong-calls'
1 Generate calls as register indirect calls, thus providing access to
1 the full 32-bit address range.
1
1 '-mmedium-calls'
1 Don't use less than 25-bit addressing range for calls, which is the
1 offset available for an unconditional branch-and-link instruction.
1 Conditional execution of function calls is suppressed, to allow use
1 of the 25-bit range, rather than the 21-bit range with conditional
1 branch-and-link. This is the default for tool chains built for
1 'arc-linux-uclibc' and 'arceb-linux-uclibc' targets.
1
1 '-G NUM'
1 Put definitions of externally-visible data in a small data section
1 if that data is no bigger than NUM bytes. The default value of NUM
1 is 4 for any ARC configuration, or 8 when we have double load/store
1 operations.
1
1 '-mno-sdata'
1 Do not generate sdata references. This is the default for tool
1 chains built for 'arc-linux-uclibc' and 'arceb-linux-uclibc'
1 targets.
1
1 '-mvolatile-cache'
1 Use ordinarily cached memory accesses for volatile references.
1 This is the default.
1
1 '-mno-volatile-cache'
1 Enable cache bypass for volatile references.
1
1 The following options fine tune code generation:
1 '-malign-call'
1 Do alignment optimizations for call instructions.
1
1 '-mauto-modify-reg'
1 Enable the use of pre/post modify with register displacement.
1
1 '-mbbit-peephole'
1 Enable bbit peephole2.
1
1 '-mno-brcc'
1 This option disables a target-specific pass in 'arc_reorg' to
1 generate compare-and-branch ('brCC') instructions. It has no
1 effect on generation of these instructions driven by the combiner
1 pass.
1
1 '-mcase-vector-pcrel'
1 Use PC-relative switch case tables to enable case table shortening.
1 This is the default for '-Os'.
1
1 '-mcompact-casesi'
1 Enable compact 'casesi' pattern. This is the default for '-Os',
1 and only available for ARCv1 cores.
1
1 '-mno-cond-exec'
1 Disable the ARCompact-specific pass to generate conditional
1 execution instructions.
1
1 Due to delay slot scheduling and interactions between operand
1 numbers, literal sizes, instruction lengths, and the support for
1 conditional execution, the target-independent pass to generate
1 conditional execution is often lacking, so the ARC port has kept a
1 special pass around that tries to find more conditional execution
1 generation opportunities after register allocation, branch
1 shortening, and delay slot scheduling have been done. This pass
1 generally, but not always, improves performance and code size, at
1 the cost of extra compilation time, which is why there is an option
1 to switch it off. If you have a problem with call instructions
1 exceeding their allowable offset range because they are
1 conditionalized, you should consider using '-mmedium-calls'
1 instead.
1
1 '-mearly-cbranchsi'
1 Enable pre-reload use of the 'cbranchsi' pattern.
1
1 '-mexpand-adddi'
1 Expand 'adddi3' and 'subdi3' at RTL generation time into 'add.f',
1 'adc' etc. This option is deprecated.
1
1 '-mindexed-loads'
1 Enable the use of indexed loads. This can be problematic because
1 some optimizers then assume that indexed stores exist, which is not
1 the case.
1
1 '-mlra'
1 Enable Local Register Allocation. This is still experimental for
1 ARC, so by default the compiler uses standard reload (i.e.
1 '-mno-lra').
1
1 '-mlra-priority-none'
1 Don't indicate any priority for target registers.
1
1 '-mlra-priority-compact'
1 Indicate target register priority for r0..r3 / r12..r15.
1
1 '-mlra-priority-noncompact'
1 Reduce target register priority for r0..r3 / r12..r15.
1
1 '-mno-millicode'
1 When optimizing for size (using '-Os'), prologues and epilogues
1 that have to save or restore a large number of registers are often
1 shortened by using call to a special function in libgcc; this is
1 referred to as a _millicode_ call. As these calls can pose
1 performance issues, and/or cause linking issues when linking in a
1 nonstandard way, this option is provided to turn off millicode call
1 generation.
1
1 '-mmixed-code'
1 Tweak register allocation to help 16-bit instruction generation.
1 This generally has the effect of decreasing the average instruction
1 size while increasing the instruction count.
1
1 '-mq-class'
1 Enable 'q' instruction alternatives. This is the default for
1 '-Os'.
1
1 '-mRcq'
1 Enable 'Rcq' constraint handling. Most short code generation
1 depends on this. This is the default.
1
1 '-mRcw'
1 Enable 'Rcw' constraint handling. Most ccfsm condexec mostly
1 depends on this. This is the default.
1
1 '-msize-level=LEVEL'
1 Fine-tune size optimization with regards to instruction lengths and
1 alignment. The recognized values for LEVEL are:
1 '0'
1 No size optimization. This level is deprecated and treated
1 like '1'.
1
1 '1'
1 Short instructions are used opportunistically.
1
1 '2'
1 In addition, alignment of loops and of code after barriers are
1 dropped.
1
1 '3'
1 In addition, optional data alignment is dropped, and the
1 option 'Os' is enabled.
1
1 This defaults to '3' when '-Os' is in effect. Otherwise, the
1 behavior when this is not set is equivalent to level '1'.
1
1 '-mtune=CPU'
1 Set instruction scheduling parameters for CPU, overriding any
1 implied by '-mcpu='.
1
1 Supported values for CPU are
1
1 'ARC600'
1 Tune for ARC600 CPU.
1
1 'ARC601'
1 Tune for ARC601 CPU.
1
1 'ARC700'
1 Tune for ARC700 CPU with standard multiplier block.
1
1 'ARC700-xmac'
1 Tune for ARC700 CPU with XMAC block.
1
1 'ARC725D'
1 Tune for ARC725D CPU.
1
1 'ARC750D'
1 Tune for ARC750D CPU.
1
1 '-mmultcost=NUM'
1 Cost to assume for a multiply instruction, with '4' being equal to
1 a normal instruction.
1
1 '-munalign-prob-threshold=PROBABILITY'
1 Set probability threshold for unaligning branches. When tuning for
1 'ARC700' and optimizing for speed, branches without filled delay
1 slot are preferably emitted unaligned and long, unless profiling
1 indicates that the probability for the branch to be taken is below
1 PROBABILITY. ⇒Cross-profiling. The default is
1 (REG_BR_PROB_BASE/2), i.e. 5000.
1
1 The following options are maintained for backward compatibility, but
1 are now deprecated and will be removed in a future release:
1
1 '-margonaut'
1 Obsolete FPX.
1
1 '-mbig-endian'
1 '-EB'
1 Compile code for big-endian targets. Use of these options is now
1 deprecated. Big-endian code is supported by configuring GCC to
1 build 'arceb-elf32' and 'arceb-linux-uclibc' targets, for which big
1 endian is the default.
1
1 '-mlittle-endian'
1 '-EL'
1 Compile code for little-endian targets. Use of these options is
1 now deprecated. Little-endian code is supported by configuring GCC
1 to build 'arc-elf32' and 'arc-linux-uclibc' targets, for which
1 little endian is the default.
1
1 '-mbarrel_shifter'
1 Replaced by '-mbarrel-shifter'.
1
1 '-mdpfp_compact'
1 Replaced by '-mdpfp-compact'.
1
1 '-mdpfp_fast'
1 Replaced by '-mdpfp-fast'.
1
1 '-mdsp_packa'
1 Replaced by '-mdsp-packa'.
1
1 '-mEA'
1 Replaced by '-mea'.
1
1 '-mmac_24'
1 Replaced by '-mmac-24'.
1
1 '-mmac_d16'
1 Replaced by '-mmac-d16'.
1
1 '-mspfp_compact'
1 Replaced by '-mspfp-compact'.
1
1 '-mspfp_fast'
1 Replaced by '-mspfp-fast'.
1
1 '-mtune=CPU'
1 Values 'arc600', 'arc601', 'arc700' and 'arc700-xmac' for CPU are
1 replaced by 'ARC600', 'ARC601', 'ARC700' and 'ARC700-xmac'
1 respectively.
1
1 '-multcost=NUM'
1 Replaced by '-mmultcost'.
1