gcc: ARM Options
1
1 3.18.4 ARM Options
1 ------------------
1
1 These '-m' options are defined for the ARM port:
1
1 '-mabi=NAME'
1 Generate code for the specified ABI. Permissible values are:
1 'apcs-gnu', 'atpcs', 'aapcs', 'aapcs-linux' and 'iwmmxt'.
1
1 '-mapcs-frame'
1 Generate a stack frame that is compliant with the ARM Procedure
1 Call Standard for all functions, even if this is not strictly
1 necessary for correct execution of the code. Specifying
1 '-fomit-frame-pointer' with this option causes the stack frames not
1 to be generated for leaf functions. The default is
1 '-mno-apcs-frame'. This option is deprecated.
1
1 '-mapcs'
1 This is a synonym for '-mapcs-frame' and is deprecated.
1
1 '-mthumb-interwork'
1 Generate code that supports calling between the ARM and Thumb
1 instruction sets. Without this option, on pre-v5 architectures,
1 the two instruction sets cannot be reliably used inside one
1 program. The default is '-mno-thumb-interwork', since slightly
1 larger code is generated when '-mthumb-interwork' is specified. In
1 AAPCS configurations this option is meaningless.
1
1 '-mno-sched-prolog'
1 Prevent the reordering of instructions in the function prologue, or
1 the merging of those instruction with the instructions in the
1 function's body. This means that all functions start with a
1 recognizable set of instructions (or in fact one of a choice from a
1 small set of different function prologues), and this information
1 can be used to locate the start of functions inside an executable
1 piece of code. The default is '-msched-prolog'.
1
1 '-mfloat-abi=NAME'
1 Specifies which floating-point ABI to use. Permissible values are:
1 'soft', 'softfp' and 'hard'.
1
1 Specifying 'soft' causes GCC to generate output containing library
1 calls for floating-point operations. 'softfp' allows the
1 generation of code using hardware floating-point instructions, but
1 still uses the soft-float calling conventions. 'hard' allows
1 generation of floating-point instructions and uses FPU-specific
1 calling conventions.
1
1 The default depends on the specific target configuration. Note
1 that the hard-float and soft-float ABIs are not link-compatible;
1 you must compile your entire program with the same ABI, and link
1 with a compatible set of libraries.
1
1 '-mlittle-endian'
1 Generate code for a processor running in little-endian mode. This
1 is the default for all standard configurations.
1
1 '-mbig-endian'
1 Generate code for a processor running in big-endian mode; the
1 default is to compile code for a little-endian processor.
1
1 '-mbe8'
1 '-mbe32'
1 When linking a big-endian image select between BE8 and BE32
1 formats. The option has no effect for little-endian images and is
1 ignored. The default is dependent on the selected target
1 architecture. For ARMv6 and later architectures the default is
1 BE8, for older architectures the default is BE32. BE32 format has
1 been deprecated by ARM.
1
1 '-march=NAME[+extension...]'
1 This specifies the name of the target ARM architecture. GCC uses
1 this name to determine what kind of instructions it can emit when
1 generating assembly code. This option can be used in conjunction
1 with or instead of the '-mcpu=' option.
1
1 Permissible names are: 'armv4t', 'armv5t', 'armv5te', 'armv6',
1 'armv6j', 'armv6k', 'armv6kz', 'armv6t2', 'armv6z', 'armv6zk',
1 'armv7', 'armv7-a', 'armv7ve', 'armv8-a', 'armv8.1-a', 'armv8.2-a',
1 'armv8.3-a', 'armv8.4-a', 'armv7-r', 'armv8-r', 'armv6-m',
1 'armv6s-m', 'armv7-m', 'armv7e-m', 'armv8-m.base', 'armv8-m.main',
1 'iwmmxt' and 'iwmmxt2'.
1
1 Additionally, the following architectures, which lack support for
1 the Thumb execution state, are recognized but support is
1 deprecated: 'armv2', 'armv2a', 'armv3', 'armv3m', 'armv4', 'armv5'
1 and 'armv5e'.
1
1 Many of the architectures support extensions. These can be added
1 by appending '+EXTENSION' to the architecture name. Extension
1 options are processed in order and capabilities accumulate. An
1 extension will also enable any necessary base extensions upon which
1 it depends. For example, the '+crypto' extension will always
1 enable the '+simd' extension. The exception to the additive
1 construction is for extensions that are prefixed with '+no...':
1 these extensions disable the specified option and any other
1 extensions that may depend on the presence of that extension.
1
1 For example, '-march=armv7-a+simd+nofp+vfpv4' is equivalent to
1 writing '-march=armv7-a+vfpv4' since the '+simd' option is entirely
1 disabled by the '+nofp' option that follows it.
1
1 Most extension names are generically named, but have an effect that
1 is dependent upon the architecture to which it is applied. For
1 example, the '+simd' option can be applied to both 'armv7-a' and
1 'armv8-a' architectures, but will enable the original ARMv7-A
1 Advanced SIMD (Neon) extensions for 'armv7-a' and the ARMv8-A
1 variant for 'armv8-a'.
1
1 The table below lists the supported extensions for each
1 architecture. Architectures not mentioned do not support any
1 extensions.
1
1 'armv5e'
1 'armv5te'
1 'armv6'
1 'armv6j'
1 'armv6k'
1 'armv6kz'
1 'armv6t2'
1 'armv6z'
1 'armv6zk'
1 '+fp'
1 The VFPv2 floating-point instructions. The extension
1 '+vfpv2' can be used as an alias for this extension.
1
1 '+nofp'
1 Disable the floating-point instructions.
1
1 'armv7'
1 The common subset of the ARMv7-A, ARMv7-R and ARMv7-M
1 architectures.
1 '+fp'
1 The VFPv3 floating-point instructions, with 16
1 double-precision registers. The extension '+vfpv3-d16'
1 can be used as an alias for this extension. Note that
1 floating-point is not supported by the base ARMv7-M
1 architecture, but is compatible with both the ARMv7-A and
1 ARMv7-R architectures.
1
1 '+nofp'
1 Disable the floating-point instructions.
1
1 'armv7-a'
1 '+mp'
1 The multiprocessing extension.
1
1 '+sec'
1 The security extension.
1
1 '+fp'
1 The VFPv3 floating-point instructions, with 16
1 double-precision registers. The extension '+vfpv3-d16'
1 can be used as an alias for this extension.
1
1 '+simd'
1 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point
1 instructions. The extensions '+neon' and '+neon-vfpv3'
1 can be used as aliases for this extension.
1
1 '+vfpv3'
1 The VFPv3 floating-point instructions, with 32
1 double-precision registers.
1
1 '+vfpv3-d16-fp16'
1 The VFPv3 floating-point instructions, with 16
1 double-precision registers and the half-precision
1 floating-point conversion operations.
1
1 '+vfpv3-fp16'
1 The VFPv3 floating-point instructions, with 32
1 double-precision registers and the half-precision
1 floating-point conversion operations.
1
1 '+vfpv4-d16'
1 The VFPv4 floating-point instructions, with 16
1 double-precision registers.
1
1 '+vfpv4'
1 The VFPv4 floating-point instructions, with 32
1 double-precision registers.
1
1 '+neon-fp16'
1 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point
1 instructions, with the half-precision floating-point
1 conversion operations.
1
1 '+neon-vfpv4'
1 The Advanced SIMD (Neon) v2 and the VFPv4 floating-point
1 instructions.
1
1 '+nosimd'
1 Disable the Advanced SIMD instructions (does not disable
1 floating point).
1
1 '+nofp'
1 Disable the floating-point and Advanced SIMD
1 instructions.
1
1 'armv7ve'
1 The extended version of the ARMv7-A architecture with support
1 for virtualization.
1 '+fp'
1 The VFPv4 floating-point instructions, with 16
1 double-precision registers. The extension '+vfpv4-d16'
1 can be used as an alias for this extension.
1
1 '+simd'
1 The Advanced SIMD (Neon) v2 and the VFPv4 floating-point
1 instructions. The extension '+neon-vfpv4' can be used as
1 an alias for this extension.
1
1 '+vfpv3-d16'
1 The VFPv3 floating-point instructions, with 16
1 double-precision registers.
1
1 '+vfpv3'
1 The VFPv3 floating-point instructions, with 32
1 double-precision registers.
1
1 '+vfpv3-d16-fp16'
1 The VFPv3 floating-point instructions, with 16
1 double-precision registers and the half-precision
1 floating-point conversion operations.
1
1 '+vfpv3-fp16'
1 The VFPv3 floating-point instructions, with 32
1 double-precision registers and the half-precision
1 floating-point conversion operations.
1
1 '+vfpv4-d16'
1 The VFPv4 floating-point instructions, with 16
1 double-precision registers.
1
1 '+vfpv4'
1 The VFPv4 floating-point instructions, with 32
1 double-precision registers.
1
1 '+neon'
1 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point
1 instructions. The extension '+neon-vfpv3' can be used as
1 an alias for this extension.
1
1 '+neon-fp16'
1 The Advanced SIMD (Neon) v1 and the VFPv3 floating-point
1 instructions, with the half-precision floating-point
1 conversion operations.
1
1 '+nosimd'
1 Disable the Advanced SIMD instructions (does not disable
1 floating point).
1
1 '+nofp'
1 Disable the floating-point and Advanced SIMD
1 instructions.
1
1 'armv8-a'
1 '+crc'
1 The Cyclic Redundancy Check (CRC) instructions.
1 '+simd'
1 The ARMv8-A Advanced SIMD and floating-point
1 instructions.
1 '+crypto'
1 The cryptographic instructions.
1 '+nocrypto'
1 Disable the cryptographic instructions.
1 '+nofp'
1 Disable the floating-point, Advanced SIMD and
1 cryptographic instructions.
1
1 'armv8.1-a'
1 '+simd'
1 The ARMv8.1-A Advanced SIMD and floating-point
1 instructions.
1
1 '+crypto'
1 The cryptographic instructions. This also enables the
1 Advanced SIMD and floating-point instructions.
1
1 '+nocrypto'
1 Disable the cryptographic instructions.
1
1 '+nofp'
1 Disable the floating-point, Advanced SIMD and
1 cryptographic instructions.
1
1 'armv8.2-a'
1 'armv8.3-a'
1 '+fp16'
1 The half-precision floating-point data processing
1 instructions. This also enables the Advanced SIMD and
1 floating-point instructions.
1
1 '+fp16fml'
1 The half-precision floating-point fmla extension. This
1 also enables the half-precision floating-point extension
1 and Advanced SIMD and floating-point instructions.
1
1 '+simd'
1 The ARMv8.1-A Advanced SIMD and floating-point
1 instructions.
1
1 '+crypto'
1 The cryptographic instructions. This also enables the
1 Advanced SIMD and floating-point instructions.
1
1 '+dotprod'
1 Enable the Dot Product extension. This also enables
1 Advanced SIMD instructions.
1
1 '+nocrypto'
1 Disable the cryptographic extension.
1
1 '+nofp'
1 Disable the floating-point, Advanced SIMD and
1 cryptographic instructions.
1
1 'armv8.4-a'
1 '+fp16'
1 The half-precision floating-point data processing
1 instructions. This also enables the Advanced SIMD and
1 floating-point instructions as well as the Dot Product
1 extension and the half-precision floating-point fmla
1 extension.
1
1 '+simd'
1 The ARMv8.3-A Advanced SIMD and floating-point
1 instructions as well as the Dot Product extension.
1
1 '+crypto'
1 The cryptographic instructions. This also enables the
1 Advanced SIMD and floating-point instructions as well as
1 the Dot Product extension.
1
1 '+nocrypto'
1 Disable the cryptographic extension.
1
1 '+nofp'
1 Disable the floating-point, Advanced SIMD and
1 cryptographic instructions.
1
1 'armv7-r'
1 '+fp.sp'
1 The single-precision VFPv3 floating-point instructions.
1 The extension '+vfpv3xd' can be used as an alias for this
1 extension.
1
1 '+fp'
1 The VFPv3 floating-point instructions with 16
1 double-precision registers. The extension +vfpv3-d16 can
1 be used as an alias for this extension.
1
1 '+vfpv3xd-d16-fp16'
1 The single-precision VFPv3 floating-point instructions
1 with 16 double-precision registers and the half-precision
1 floating-point conversion operations.
1
1 '+vfpv3-d16-fp16'
1 The VFPv3 floating-point instructions, with 16
1 double-precision registers and the half-precision
1 floating-point conversion operations.
1
1 '+nofp'
1 Disable the floating-point extension.
1
1 '+idiv'
1 The ARM-state integer division instructions.
1
1 '+noidiv'
1 Disable the ARM-state integer division extension.
1
1 'armv7e-m'
1 '+fp'
1 The single-precision VFPv4 floating-point instructions.
1
1 '+fpv5'
1 The single-precision FPv5 floating-point instructions.
1
1 '+fp.dp'
1 The single- and double-precision FPv5 floating-point
1 instructions.
1
1 '+nofp'
1 Disable the floating-point extensions.
1
1 'armv8-m.main'
1 '+dsp'
1 The DSP instructions.
1
1 '+nodsp'
1 Disable the DSP extension.
1
1 '+fp'
1 The single-precision floating-point instructions.
1
1 '+fp.dp'
1 The single- and double-precision floating-point
1 instructions.
1
1 '+nofp'
1 Disable the floating-point extension.
1
1 'armv8-r'
1 '+crc'
1 The Cyclic Redundancy Check (CRC) instructions.
1 '+fp.sp'
1 The single-precision FPv5 floating-point instructions.
1 '+simd'
1 The ARMv8-A Advanced SIMD and floating-point
1 instructions.
1 '+crypto'
1 The cryptographic instructions.
1 '+nocrypto'
1 Disable the cryptographic instructions.
1 '+nofp'
1 Disable the floating-point, Advanced SIMD and
1 cryptographic instructions.
1
1 '-march=native' causes the compiler to auto-detect the architecture
1 of the build computer. At present, this feature is only supported
1 on GNU/Linux, and not all architectures are recognized. If the
1 auto-detect is unsuccessful the option has no effect.
1
1 '-mtune=NAME'
1 This option specifies the name of the target ARM processor for
1 which GCC should tune the performance of the code. For some ARM
1 implementations better performance can be obtained by using this
1 option. Permissible names are: 'arm2', 'arm250', 'arm3', 'arm6',
1 'arm60', 'arm600', 'arm610', 'arm620', 'arm7', 'arm7m', 'arm7d',
1 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700', 'arm700i',
1 'arm710', 'arm710c', 'arm7100', 'arm720', 'arm7500', 'arm7500fe',
1 'arm7tdmi', 'arm7tdmi-s', 'arm710t', 'arm720t', 'arm740t',
1 'strongarm', 'strongarm110', 'strongarm1100', 'strongarm1110',
1 'arm8', 'arm810', 'arm9', 'arm9e', 'arm920', 'arm920t', 'arm922t',
1 'arm946e-s', 'arm966e-s', 'arm968e-s', 'arm926ej-s', 'arm940t',
1 'arm9tdmi', 'arm10tdmi', 'arm1020t', 'arm1026ej-s', 'arm10e',
1 'arm1020e', 'arm1022e', 'arm1136j-s', 'arm1136jf-s', 'mpcore',
1 'mpcorenovfp', 'arm1156t2-s', 'arm1156t2f-s', 'arm1176jz-s',
1 'arm1176jzf-s', 'generic-armv7-a', 'cortex-a5', 'cortex-a7',
1 'cortex-a8', 'cortex-a9', 'cortex-a12', 'cortex-a15', 'cortex-a17',
1 'cortex-a32', 'cortex-a35', 'cortex-a53', 'cortex-a55',
1 'cortex-a57', 'cortex-a72', 'cortex-a73', 'cortex-a75',
1 'neoverse-v1', 'neoverse-n2', 'cortex-r4', 'cortex-r4f',
1 'cortex-r5', 'cortex-r7', 'cortex-r8', 'cortex-r52', 'cortex-m33',
1 'cortex-m23', 'cortex-m7', 'cortex-m4', 'cortex-m3', 'cortex-m1',
1 'cortex-m0', 'cortex-m0plus', 'cortex-m1.small-multiply',
1 'cortex-m0.small-multiply', 'cortex-m0plus.small-multiply',
1 'exynos-m1', 'marvell-pj4', 'xscale', 'iwmmxt', 'iwmmxt2',
1 'ep9312', 'fa526', 'fa626', 'fa606te', 'fa626te', 'fmp626',
1 'fa726te', 'xgene1'.
1
1 Additionally, this option can specify that GCC should tune the
1 performance of the code for a big.LITTLE system. Permissible names
1 are: 'cortex-a15.cortex-a7', 'cortex-a17.cortex-a7',
1 'cortex-a57.cortex-a53', 'cortex-a72.cortex-a53',
1 'cortex-a72.cortex-a35', 'cortex-a73.cortex-a53',
1 'cortex-a75.cortex-a55'.
1
1 '-mtune=generic-ARCH' specifies that GCC should tune the
1 performance for a blend of processors within architecture ARCH.
1 The aim is to generate code that run well on the current most
1 popular processors, balancing between optimizations that benefit
1 some CPUs in the range, and avoiding performance pitfalls of other
1 CPUs. The effects of this option may change in future GCC versions
1 as CPU models come and go.
1
1 '-mtune' permits the same extension options as '-mcpu', but the
1 extension options do not affect the tuning of the generated code.
1
1 '-mtune=native' causes the compiler to auto-detect the CPU of the
1 build computer. At present, this feature is only supported on
1 GNU/Linux, and not all architectures are recognized. If the
1 auto-detect is unsuccessful the option has no effect.
1
1 '-mcpu=NAME[+extension...]'
1 This specifies the name of the target ARM processor. GCC uses this
1 name to derive the name of the target ARM architecture (as if
1 specified by '-march') and the ARM processor type for which to tune
1 for performance (as if specified by '-mtune'). Where this option
1 is used in conjunction with '-march' or '-mtune', those options
1 take precedence over the appropriate part of this option.
1
1 Many of the supported CPUs implement optional architectural
1 extensions. Where this is so the architectural extensions are
1 normally enabled by default. If implementations that lack the
1 extension exist, then the extension syntax can be used to disable
1 those extensions that have been omitted. For floating-point and
1 Advanced SIMD (Neon) instructions, the settings of the options
1 '-mfloat-abi' and '-mfpu' must also be considered: floating-point
1 and Advanced SIMD instructions will only be used if '-mfloat-abi'
1 is not set to 'soft'; and any setting of '-mfpu' other than 'auto'
1 will override the available floating-point and SIMD extension
1 instructions.
1
1 For example, 'cortex-a9' can be found in three major
1 configurations: integer only, with just a floating-point unit or
1 with floating-point and Advanced SIMD. The default is to enable all
1 the instructions, but the extensions '+nosimd' and '+nofp' can be
1 used to disable just the SIMD or both the SIMD and floating-point
1 instructions respectively.
1
1 Permissible names for this option are the same as those for
1 '-mtune'.
1
1 The following extension options are common to the listed CPUs:
1
1 '+nodsp'
1 Disable the DSP instructions on 'cortex-m33'.
1
1 '+nofp'
1 Disables the floating-point instructions on 'arm9e',
1 'arm946e-s', 'arm966e-s', 'arm968e-s', 'arm10e', 'arm1020e',
1 'arm1022e', 'arm926ej-s', 'arm1026ej-s', 'cortex-r5',
1 'cortex-r7', 'cortex-r8', 'cortex-m4', 'cortex-m7' and
1 'cortex-m33'. Disables the floating-point and SIMD
1 instructions on 'generic-armv7-a', 'cortex-a5', 'cortex-a7',
1 'cortex-a8', 'cortex-a9', 'cortex-a12', 'cortex-a15',
1 'cortex-a17', 'cortex-a15.cortex-a7', 'cortex-a17.cortex-a7',
1 'cortex-a32', 'cortex-a35', 'cortex-a53' and 'cortex-a55'.
1
1 '+nofp.dp'
1 Disables the double-precision component of the floating-point
1 instructions on 'cortex-r5', 'cortex-r7', 'cortex-r8',
1 'cortex-r52' and 'cortex-m7'.
1
1 '+nosimd'
1 Disables the SIMD (but not floating-point) instructions on
1 'generic-armv7-a', 'cortex-a5', 'cortex-a7' and 'cortex-a9'.
1
1 '+crypto'
1 Enables the cryptographic instructions on 'cortex-a32',
1 'cortex-a35', 'cortex-a53', 'cortex-a55', 'cortex-a57',
1 'cortex-a72', 'cortex-a73', 'cortex-a75', 'exynos-m1',
1 'xgene1', 'cortex-a57.cortex-a53', 'cortex-a72.cortex-a53',
1 'cortex-a73.cortex-a35', 'cortex-a73.cortex-a53' and
1 'cortex-a75.cortex-a55'.
1
1 Additionally the 'generic-armv7-a' pseudo target defaults to VFPv3
1 with 16 double-precision registers. It supports the following
1 extension options: 'mp', 'sec', 'vfpv3-d16', 'vfpv3',
1 'vfpv3-d16-fp16', 'vfpv3-fp16', 'vfpv4-d16', 'vfpv4', 'neon',
1 'neon-vfpv3', 'neon-fp16', 'neon-vfpv4'. The meanings are the same
1 as for the extensions to '-march=armv7-a'.
1
1 '-mcpu=generic-ARCH' is also permissible, and is equivalent to
1 '-march=ARCH -mtune=generic-ARCH'. See '-mtune' for more
1 information.
1
1 '-mcpu=native' causes the compiler to auto-detect the CPU of the
1 build computer. At present, this feature is only supported on
1 GNU/Linux, and not all architectures are recognized. If the
1 auto-detect is unsuccessful the option has no effect.
1
1 '-mfpu=NAME'
1 This specifies what floating-point hardware (or hardware emulation)
1 is available on the target. Permissible names are: 'auto',
1 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16', 'vfpv3-d16-fp16',
1 'vfpv3xd', 'vfpv3xd-fp16', 'neon-vfpv3', 'neon-fp16', 'vfpv4',
1 'vfpv4-d16', 'fpv4-sp-d16', 'neon-vfpv4', 'fpv5-d16',
1 'fpv5-sp-d16', 'fp-armv8', 'neon-fp-armv8' and
1 'crypto-neon-fp-armv8'. Note that 'neon' is an alias for
1 'neon-vfpv3' and 'vfp' is an alias for 'vfpv2'.
1
1 The setting 'auto' is the default and is special. It causes the
1 compiler to select the floating-point and Advanced SIMD
1 instructions based on the settings of '-mcpu' and '-march'.
1
1 If the selected floating-point hardware includes the NEON extension
1 (e.g. '-mfpu=neon'), note that floating-point operations are not
1 generated by GCC's auto-vectorization pass unless
1 '-funsafe-math-optimizations' is also specified. This is because
1 NEON hardware does not fully implement the IEEE 754 standard for
1 floating-point arithmetic (in particular denormal values are
1 treated as zero), so the use of NEON instructions may lead to a
1 loss of precision.
1
1 You can also set the fpu name at function level by using the
11 Attributes::) or pragmas (⇒Function Specific Option
Pragmas).
1
1 '-mfp16-format=NAME'
1 Specify the format of the '__fp16' half-precision floating-point
1 type. Permissible names are 'none', 'ieee', and 'alternative'; the
1 default is 'none', in which case the '__fp16' type is not defined.
1 ⇒Half-Precision, for more information.
1
1 '-mstructure-size-boundary=N'
1 The sizes of all structures and unions are rounded up to a multiple
1 of the number of bits set by this option. Permissible values are
1 8, 32 and 64. The default value varies for different toolchains.
1 For the COFF targeted toolchain the default value is 8. A value of
1 64 is only allowed if the underlying ABI supports it.
1
1 Specifying a larger number can produce faster, more efficient code,
1 but can also increase the size of the program. Different values
1 are potentially incompatible. Code compiled with one value cannot
1 necessarily expect to work with code or libraries compiled with
1 another value, if they exchange information using structures or
1 unions.
1
1 This option is deprecated.
1
1 '-mabort-on-noreturn'
1 Generate a call to the function 'abort' at the end of a 'noreturn'
1 function. It is executed if the function tries to return.
1
1 '-mlong-calls'
1 '-mno-long-calls'
1 Tells the compiler to perform function calls by first loading the
1 address of the function into a register and then performing a
1 subroutine call on this register. This switch is needed if the
1 target function lies outside of the 64-megabyte addressing range of
1 the offset-based version of subroutine call instruction.
1
1 Even if this switch is enabled, not all function calls are turned
1 into long calls. The heuristic is that static functions, functions
1 that have the 'short_call' attribute, functions that are inside the
1 scope of a '#pragma no_long_calls' directive, and functions whose
1 definitions have already been compiled within the current
1 compilation unit are not turned into long calls. The exceptions to
1 this rule are that weak function definitions, functions with the
1 'long_call' attribute or the 'section' attribute, and functions
1 that are within the scope of a '#pragma long_calls' directive are
1 always turned into long calls.
1
1 This feature is not enabled by default. Specifying
1 '-mno-long-calls' restores the default behavior, as does placing
1 the function calls within the scope of a '#pragma long_calls_off'
1 directive. Note these switches have no effect on how the compiler
1 generates code to handle function calls via function pointers.
1
1 '-msingle-pic-base'
1 Treat the register used for PIC addressing as read-only, rather
1 than loading it in the prologue for each function. The runtime
1 system is responsible for initializing this register with an
1 appropriate value before execution begins.
1
1 '-mpic-register=REG'
1 Specify the register to be used for PIC addressing. For standard
1 PIC base case, the default is any suitable register determined by
1 compiler. For single PIC base case, the default is 'R9' if target
1 is EABI based or stack-checking is enabled, otherwise the default
1 is 'R10'.
1
1 '-mpic-data-is-text-relative'
1 Assume that the displacement between the text and data segments is
1 fixed at static link time. This permits using PC-relative
1 addressing operations to access data known to be in the data
1 segment. For non-VxWorks RTP targets, this option is enabled by
1 default. When disabled on such targets, it will enable
1 '-msingle-pic-base' by default.
1
1 '-mpoke-function-name'
1 Write the name of each function into the text section, directly
1 preceding the function prologue. The generated code is similar to
1 this:
1
1 t0
1 .ascii "arm_poke_function_name", 0
1 .align
1 t1
1 .word 0xff000000 + (t1 - t0)
1 arm_poke_function_name
1 mov ip, sp
1 stmfd sp!, {fp, ip, lr, pc}
1 sub fp, ip, #4
1
1 When performing a stack backtrace, code can inspect the value of
1 'pc' stored at 'fp + 0'. If the trace function then looks at
1 location 'pc - 12' and the top 8 bits are set, then we know that
1 there is a function name embedded immediately preceding this
1 location and has length '((pc[-3]) & 0xff000000)'.
1
1 '-mthumb'
1 '-marm'
1
1 Select between generating code that executes in ARM and Thumb
1 states. The default for most configurations is to generate code
1 that executes in ARM state, but the default can be changed by
1 configuring GCC with the '--with-mode='STATE configure option.
1
1 You can also override the ARM and Thumb mode for each function by
1 using the 'target("thumb")' and 'target("arm")' function attributes
DONTPRINTYET 1 (⇒ARM Function Attributes) or pragmas (*noteFunction
1DONTPRINTYET 1 (⇒ARM Function Attributes) or pragmas (⇒Function
Specific Option Pragmas).
1
1 '-mflip-thumb'
1 Switch ARM/Thumb modes on alternating functions. This option is
1 provided for regression testing of mixed Thumb/ARM code generation,
1 and is not intended for ordinary use in compiling code.
1
1 '-mtpcs-frame'
1 Generate a stack frame that is compliant with the Thumb Procedure
1 Call Standard for all non-leaf functions. (A leaf function is one
1 that does not call any other functions.) The default is
1 '-mno-tpcs-frame'.
1
1 '-mtpcs-leaf-frame'
1 Generate a stack frame that is compliant with the Thumb Procedure
1 Call Standard for all leaf functions. (A leaf function is one that
1 does not call any other functions.) The default is
1 '-mno-apcs-leaf-frame'.
1
1 '-mcallee-super-interworking'
1 Gives all externally visible functions in the file being compiled
1 an ARM instruction set header which switches to Thumb mode before
1 executing the rest of the function. This allows these functions to
1 be called from non-interworking code. This option is not valid in
1 AAPCS configurations because interworking is enabled by default.
1
1 '-mcaller-super-interworking'
1 Allows calls via function pointers (including virtual functions) to
1 execute correctly regardless of whether the target code has been
1 compiled for interworking or not. There is a small overhead in the
1 cost of executing a function pointer if this option is enabled.
1 This option is not valid in AAPCS configurations because
1 interworking is enabled by default.
1
1 '-mtp=NAME'
1 Specify the access model for the thread local storage pointer. The
1 valid models are 'soft', which generates calls to
1 '__aeabi_read_tp', 'cp15', which fetches the thread pointer from
1 'cp15' directly (supported in the arm6k architecture), and 'auto',
1 which uses the best available method for the selected processor.
1 The default setting is 'auto'.
1
1 '-mtls-dialect=DIALECT'
1 Specify the dialect to use for accessing thread local storage. Two
1 DIALECTs are supported--'gnu' and 'gnu2'. The 'gnu' dialect
1 selects the original GNU scheme for supporting local and global
1 dynamic TLS models. The 'gnu2' dialect selects the GNU descriptor
1 scheme, which provides better performance for shared libraries.
1 The GNU descriptor scheme is compatible with the original scheme,
1 but does require new assembler, linker and library support.
1 Initial and local exec TLS models are unaffected by this option and
1 always use the original scheme.
1
1 '-mword-relocations'
1 Only generate absolute relocations on word-sized values (i.e.
1 R_ARM_ABS32). This is enabled by default on targets (uClinux,
1 SymbianOS) where the runtime loader imposes this restriction, and
1 when '-fpic' or '-fPIC' is specified.
1
1 '-mfix-cortex-m3-ldrd'
1 Some Cortex-M3 cores can cause data corruption when 'ldrd'
1 instructions with overlapping destination and base registers are
1 used. This option avoids generating these instructions. This
1 option is enabled by default when '-mcpu=cortex-m3' is specified.
1
1 '-munaligned-access'
1 '-mno-unaligned-access'
1 Enables (or disables) reading and writing of 16- and 32- bit values
1 from addresses that are not 16- or 32- bit aligned. By default
1 unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for
1 ARMv8-M Baseline architectures, and enabled for all other
1 architectures. If unaligned access is not enabled then words in
1 packed data structures are accessed a byte at a time.
1
1 The ARM attribute 'Tag_CPU_unaligned_access' is set in the
1 generated object file to either true or false, depending upon the
1 setting of this option. If unaligned access is enabled then the
1 preprocessor symbol '__ARM_FEATURE_UNALIGNED' is also defined.
1
1 '-mneon-for-64bits'
1 Enables using Neon to handle scalar 64-bits operations. This is
1 disabled by default since the cost of moving data from core
1 registers to Neon is high.
1
1 '-mslow-flash-data'
1 Assume loading data from flash is slower than fetching instruction.
1 Therefore literal load is minimized for better performance. This
1 option is only supported when compiling for ARMv7 M-profile and off
1 by default.
1
1 '-masm-syntax-unified'
1 Assume inline assembler is using unified asm syntax. The default
1 is currently off which implies divided syntax. This option has no
1 impact on Thumb2. However, this may change in future releases of
1 GCC. Divided syntax should be considered deprecated.
1
1 '-mrestrict-it'
1 Restricts generation of IT blocks to conform to the rules of
1 ARMv8-A. IT blocks can only contain a single 16-bit instruction
1 from a select set of instructions. This option is on by default
1 for ARMv8-A Thumb mode.
1
1 '-mprint-tune-info'
1 Print CPU tuning information as comment in assembler file. This is
1 an option used only for regression testing of the compiler and not
1 intended for ordinary use in compiling code. This option is
1 disabled by default.
1
1 '-mverbose-cost-dump'
1 Enable verbose cost model dumping in the debug dump files. This
1 option is provided for use in debugging the compiler.
1
1 '-mpure-code'
1 Do not allow constant data to be placed in code sections.
1 Additionally, when compiling for ELF object format give all text
1 sections the ELF processor-specific section attribute
1 'SHF_ARM_PURECODE'. This option is only available when generating
1 non-pic code for M-profile targets with the MOVT instruction.
1
1 '-mcmse'
1 Generate secure code as per the "ARMv8-M Security Extensions:
1 Requirements on Development Tools Engineering Specification", which
1 can be found on
1 <https://developer.arm.com/documentation/ecm0359818/latest/>.
1