gccint: Machine Constraints
1
1 17.8.5 Constraints for Particular Machines
1 ------------------------------------------
1
1 Whenever possible, you should use the general-purpose constraint letters
1 in 'asm' arguments, since they will convey meaning more readily to
1 people reading your code. Failing that, use the constraint letters that
1 usually have very similar meanings across architectures. The most
1 commonly used constraints are 'm' and 'r' (for memory and
1 general-purpose registers respectively; ⇒Simple Constraints), and
1 'I', usually the letter indicating the most common immediate-constant
1 format.
1
1 Each architecture defines additional constraints. These constraints
1 are used by the compiler itself for instruction generation, as well as
1 for 'asm' statements; therefore, some of the constraints are not
1 particularly useful for 'asm'. Here is a summary of some of the
1 machine-dependent constraints available on some particular machines; it
1 includes both constraints that are useful for 'asm' and constraints that
1 aren't. The compiler source file mentioned in the table heading for
1 each architecture is the definitive reference for the meanings of that
1 architecture's constraints.
1
1 _AArch64 family--'config/aarch64/constraints.md'_
1 'k'
1 The stack pointer register ('SP')
1
1 'w'
1 Floating point register, Advanced SIMD vector register or SVE
1 vector register
1
1 'Upl'
1 One of the low eight SVE predicate registers ('P0' to 'P7')
1
1 'Upa'
1 Any of the SVE predicate registers ('P0' to 'P15')
1
1 'I'
1 Integer constant that is valid as an immediate operand in an
1 'ADD' instruction
1
1 'J'
1 Integer constant that is valid as an immediate operand in a
1 'SUB' instruction (once negated)
1
1 'K'
1 Integer constant that can be used with a 32-bit logical
1 instruction
1
1 'L'
1 Integer constant that can be used with a 64-bit logical
1 instruction
1
1 'M'
1 Integer constant that is valid as an immediate operand in a
1 32-bit 'MOV' pseudo instruction. The 'MOV' may be assembled
1 to one of several different machine instructions depending on
1 the value
1
1 'N'
1 Integer constant that is valid as an immediate operand in a
1 64-bit 'MOV' pseudo instruction
1
1 'S'
1 An absolute symbolic address or a label reference
1
1 'Y'
1 Floating point constant zero
1
1 'Z'
1 Integer constant zero
1
1 'Ush'
1 The high part (bits 12 and upwards) of the pc-relative address
1 of a symbol within 4GB of the instruction
1
1 'Q'
1 A memory address which uses a single base register with no
1 offset
1
1 'Ump'
1 A memory address suitable for a load/store pair instruction in
1 SI, DI, SF and DF modes
1
1 _ARC --'config/arc/constraints.md'_
1 'q'
1 Registers usable in ARCompact 16-bit instructions: 'r0'-'r3',
1 'r12'-'r15'. This constraint can only match when the '-mq'
1 option is in effect.
1
1 'e'
1 Registers usable as base-regs of memory addresses in ARCompact
1 16-bit memory instructions: 'r0'-'r3', 'r12'-'r15', 'sp'.
1 This constraint can only match when the '-mq' option is in
1 effect.
1 'D'
1 ARC FPX (dpfp) 64-bit registers. 'D0', 'D1'.
1
1 'I'
1 A signed 12-bit integer constant.
1
1 'Cal'
1 constant for arithmetic/logical operations. This might be any
1 constant that can be put into a long immediate by the assmbler
1 or linker without involving a PIC relocation.
1
1 'K'
1 A 3-bit unsigned integer constant.
1
1 'L'
1 A 6-bit unsigned integer constant.
1
1 'CnL'
1 One's complement of a 6-bit unsigned integer constant.
1
1 'CmL'
1 Two's complement of a 6-bit unsigned integer constant.
1
1 'M'
1 A 5-bit unsigned integer constant.
1
1 'O'
1 A 7-bit unsigned integer constant.
1
1 'P'
1 A 8-bit unsigned integer constant.
1
1 'H'
1 Any const_double value.
1
1 _ARM family--'config/arm/constraints.md'_
1
1 'h'
1 In Thumb state, the core registers 'r8'-'r15'.
1
1 'k'
1 The stack pointer register.
1
1 'l'
1 In Thumb State the core registers 'r0'-'r7'. In ARM state
1 this is an alias for the 'r' constraint.
1
1 't'
1 VFP floating-point registers 's0'-'s31'. Used for 32 bit
1 values.
1
1 'w'
1 VFP floating-point registers 'd0'-'d31' and the appropriate
1 subset 'd0'-'d15' based on command line options. Used for 64
1 bit values only. Not valid for Thumb1.
1
1 'y'
1 The iWMMX co-processor registers.
1
1 'z'
1 The iWMMX GR registers.
1
1 'G'
1 The floating-point constant 0.0
1
1 'I'
1 Integer that is valid as an immediate operand in a data
1 processing instruction. That is, an integer in the range 0 to
1 255 rotated by a multiple of 2
1
1 'J'
1 Integer in the range -4095 to 4095
1
1 'K'
1 Integer that satisfies constraint 'I' when inverted (ones
1 complement)
1
1 'L'
1 Integer that satisfies constraint 'I' when negated (twos
1 complement)
1
1 'M'
1 Integer in the range 0 to 32
1
1 'Q'
1 A memory reference where the exact address is in a single
1 register (''m'' is preferable for 'asm' statements)
1
1 'R'
1 An item in the constant pool
1
1 'S'
1 A symbol in the text segment of the current file
1
1 'Uv'
1 A memory reference suitable for VFP load/store insns
1 (reg+constant offset)
1
1 'Uy'
1 A memory reference suitable for iWMMXt load/store
1 instructions.
1
1 'Uq'
1 A memory reference suitable for the ARMv4 ldrsb instruction.
1
1 _AVR family--'config/avr/constraints.md'_
1 'l'
1 Registers from r0 to r15
1
1 'a'
1 Registers from r16 to r23
1
1 'd'
1 Registers from r16 to r31
1
1 'w'
1 Registers from r24 to r31. These registers can be used in
1 'adiw' command
1
1 'e'
1 Pointer register (r26-r31)
1
1 'b'
1 Base pointer register (r28-r31)
1
1 'q'
1 Stack pointer register (SPH:SPL)
1
1 't'
1 Temporary register r0
1
1 'x'
1 Register pair X (r27:r26)
1
1 'y'
1 Register pair Y (r29:r28)
1
1 'z'
1 Register pair Z (r31:r30)
1
1 'I'
1 Constant greater than -1, less than 64
1
1 'J'
1 Constant greater than -64, less than 1
1
1 'K'
1 Constant integer 2
1
1 'L'
1 Constant integer 0
1
1 'M'
1 Constant that fits in 8 bits
1
1 'N'
1 Constant integer -1
1
1 'O'
1 Constant integer 8, 16, or 24
1
1 'P'
1 Constant integer 1
1
1 'G'
1 A floating point constant 0.0
1
1 'Q'
1 A memory address based on Y or Z pointer with displacement.
1
1 _Blackfin family--'config/bfin/constraints.md'_
1 'a'
1 P register
1
1 'd'
1 D register
1
1 'z'
1 A call clobbered P register.
1
1 'qN'
1 A single register. If N is in the range 0 to 7, the
1 corresponding D register. If it is 'A', then the register P0.
1
1 'D'
1 Even-numbered D register
1
1 'W'
1 Odd-numbered D register
1
1 'e'
1 Accumulator register.
1
1 'A'
1 Even-numbered accumulator register.
1
1 'B'
1 Odd-numbered accumulator register.
1
1 'b'
1 I register
1
1 'v'
1 B register
1
1 'f'
1 M register
1
1 'c'
1 Registers used for circular buffering, i.e. I, B, or L
1 registers.
1
1 'C'
1 The CC register.
1
1 't'
1 LT0 or LT1.
1
1 'k'
1 LC0 or LC1.
1
1 'u'
1 LB0 or LB1.
1
1 'x'
1 Any D, P, B, M, I or L register.
1
1 'y'
1 Additional registers typically used only in prologues and
1 epilogues: RETS, RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and
1 USP.
1
1 'w'
1 Any register except accumulators or CC.
1
1 'Ksh'
1 Signed 16 bit integer (in the range -32768 to 32767)
1
1 'Kuh'
1 Unsigned 16 bit integer (in the range 0 to 65535)
1
1 'Ks7'
1 Signed 7 bit integer (in the range -64 to 63)
1
1 'Ku7'
1 Unsigned 7 bit integer (in the range 0 to 127)
1
1 'Ku5'
1 Unsigned 5 bit integer (in the range 0 to 31)
1
1 'Ks4'
1 Signed 4 bit integer (in the range -8 to 7)
1
1 'Ks3'
1 Signed 3 bit integer (in the range -3 to 4)
1
1 'Ku3'
1 Unsigned 3 bit integer (in the range 0 to 7)
1
1 'PN'
1 Constant N, where N is a single-digit constant in the range 0
1 to 4.
1
1 'PA'
1 An integer equal to one of the MACFLAG_XXX constants that is
1 suitable for use with either accumulator.
1
1 'PB'
1 An integer equal to one of the MACFLAG_XXX constants that is
1 suitable for use only with accumulator A1.
1
1 'M1'
1 Constant 255.
1
1 'M2'
1 Constant 65535.
1
1 'J'
1 An integer constant with exactly a single bit set.
1
1 'L'
1 An integer constant with all bits set except exactly one.
1
1 'H'
1
1 'Q'
1 Any SYMBOL_REF.
1
1 _CR16 Architecture--'config/cr16/cr16.h'_
1
1 'b'
1 Registers from r0 to r14 (registers without stack pointer)
1
1 't'
1 Register from r0 to r11 (all 16-bit registers)
1
1 'p'
1 Register from r12 to r15 (all 32-bit registers)
1
1 'I'
1 Signed constant that fits in 4 bits
1
1 'J'
1 Signed constant that fits in 5 bits
1
1 'K'
1 Signed constant that fits in 6 bits
1
1 'L'
1 Unsigned constant that fits in 4 bits
1
1 'M'
1 Signed constant that fits in 32 bits
1
1 'N'
1 Check for 64 bits wide constants for add/sub instructions
1
1 'G'
1 Floating point constant that is legal for store immediate
1
1 _Epiphany--'config/epiphany/constraints.md'_
1 'U16'
1 An unsigned 16-bit constant.
1
1 'K'
1 An unsigned 5-bit constant.
1
1 'L'
1 A signed 11-bit constant.
1
1 'Cm1'
1 A signed 11-bit constant added to -1. Can only match when the
1 '-m1reg-REG' option is active.
1
1 'Cl1'
1 Left-shift of -1, i.e., a bit mask with a block of leading
1 ones, the rest being a block of trailing zeroes. Can only
1 match when the '-m1reg-REG' option is active.
1
1 'Cr1'
1 Right-shift of -1, i.e., a bit mask with a trailing block of
1 ones, the rest being zeroes. Or to put it another way, one
1 less than a power of two. Can only match when the
1 '-m1reg-REG' option is active.
1
1 'Cal'
1 Constant for arithmetic/logical operations. This is like 'i',
1 except that for position independent code, no symbols /
1 expressions needing relocations are allowed.
1
1 'Csy'
1 Symbolic constant for call/jump instruction.
1
1 'Rcs'
1 The register class usable in short insns. This is a register
1 class constraint, and can thus drive register allocation.
1 This constraint won't match unless '-mprefer-short-insn-regs'
1 is in effect.
1
1 'Rsc'
1 The the register class of registers that can be used to hold a
1 sibcall call address. I.e., a caller-saved register.
1
1 'Rct'
1 Core control register class.
1
1 'Rgs'
1 The register group usable in short insns. This constraint
1 does not use a register class, so that it only passively
1 matches suitable registers, and doesn't drive register
1 allocation.
1
1 'Car'
1 Constant suitable for the addsi3_r pattern. This is a valid
1 offset For byte, halfword, or word addressing.
1
1 'Rra'
1 Matches the return address if it can be replaced with the link
1 register.
1
1 'Rcc'
1 Matches the integer condition code register.
1
1 'Sra'
1 Matches the return address if it is in a stack slot.
1
1 'Cfm'
1 Matches control register values to switch fp mode, which are
1 encapsulated in 'UNSPEC_FP_MODE'.
1
1 _FRV--'config/frv/frv.h'_
1 'a'
1 Register in the class 'ACC_REGS' ('acc0' to 'acc7').
1
1 'b'
1 Register in the class 'EVEN_ACC_REGS' ('acc0' to 'acc7').
1
1 'c'
1 Register in the class 'CC_REGS' ('fcc0' to 'fcc3' and 'icc0'
1 to 'icc3').
1
1 'd'
1 Register in the class 'GPR_REGS' ('gr0' to 'gr63').
1
1 'e'
1 Register in the class 'EVEN_REGS' ('gr0' to 'gr63'). Odd
1 registers are excluded not in the class but through the use of
1 a machine mode larger than 4 bytes.
1
1 'f'
1 Register in the class 'FPR_REGS' ('fr0' to 'fr63').
1
1 'h'
1 Register in the class 'FEVEN_REGS' ('fr0' to 'fr63'). Odd
1 registers are excluded not in the class but through the use of
1 a machine mode larger than 4 bytes.
1
1 'l'
1 Register in the class 'LR_REG' (the 'lr' register).
1
1 'q'
1 Register in the class 'QUAD_REGS' ('gr2' to 'gr63'). Register
1 numbers not divisible by 4 are excluded not in the class but
1 through the use of a machine mode larger than 8 bytes.
1
1 't'
1 Register in the class 'ICC_REGS' ('icc0' to 'icc3').
1
1 'u'
1 Register in the class 'FCC_REGS' ('fcc0' to 'fcc3').
1
1 'v'
1 Register in the class 'ICR_REGS' ('cc4' to 'cc7').
1
1 'w'
1 Register in the class 'FCR_REGS' ('cc0' to 'cc3').
1
1 'x'
1 Register in the class 'QUAD_FPR_REGS' ('fr0' to 'fr63').
1 Register numbers not divisible by 4 are excluded not in the
1 class but through the use of a machine mode larger than 8
1 bytes.
1
1 'z'
1 Register in the class 'SPR_REGS' ('lcr' and 'lr').
1
1 'A'
1 Register in the class 'QUAD_ACC_REGS' ('acc0' to 'acc7').
1
1 'B'
1 Register in the class 'ACCG_REGS' ('accg0' to 'accg7').
1
1 'C'
1 Register in the class 'CR_REGS' ('cc0' to 'cc7').
1
1 'G'
1 Floating point constant zero
1
1 'I'
1 6-bit signed integer constant
1
1 'J'
1 10-bit signed integer constant
1
1 'L'
1 16-bit signed integer constant
1
1 'M'
1 16-bit unsigned integer constant
1
1 'N'
1 12-bit signed integer constant that is negative--i.e. in the
1 range of -2048 to -1
1
1 'O'
1 Constant zero
1
1 'P'
1 12-bit signed integer constant that is greater than zero--i.e.
1 in the range of 1 to 2047.
1
1 _FT32--'config/ft32/constraints.md'_
1 'A'
1 An absolute address
1
1 'B'
1 An offset address
1
1 'W'
1 A register indirect memory operand
1
1 'e'
1 An offset address.
1
1 'f'
1 An offset address.
1
1 'O'
1 The constant zero or one
1
1 'I'
1 A 16-bit signed constant (-32768 ... 32767)
1
1 'w'
1 A bitfield mask suitable for bext or bins
1
1 'x'
1 An inverted bitfield mask suitable for bext or bins
1
1 'L'
1 A 16-bit unsigned constant, multiple of 4 (0 ... 65532)
1
1 'S'
1 A 20-bit signed constant (-524288 ... 524287)
1
1 'b'
1 A constant for a bitfield width (1 ... 16)
1
1 'KA'
1 A 10-bit signed constant (-512 ... 511)
1
1 _Hewlett-Packard PA-RISC--'config/pa/pa.h'_
1 'a'
1 General register 1
1
1 'f'
1 Floating point register
1
1 'q'
1 Shift amount register
1
1 'x'
1 Floating point register (deprecated)
1
1 'y'
1 Upper floating point register (32-bit), floating point
1 register (64-bit)
1
1 'Z'
1 Any register
1
1 'I'
1 Signed 11-bit integer constant
1
1 'J'
1 Signed 14-bit integer constant
1
1 'K'
1 Integer constant that can be deposited with a 'zdepi'
1 instruction
1
1 'L'
1 Signed 5-bit integer constant
1
1 'M'
1 Integer constant 0
1
1 'N'
1 Integer constant that can be loaded with a 'ldil' instruction
1
1 'O'
1 Integer constant whose value plus one is a power of 2
1
1 'P'
1 Integer constant that can be used for 'and' operations in
1 'depi' and 'extru' instructions
1
1 'S'
1 Integer constant 31
1
1 'U'
1 Integer constant 63
1
1 'G'
1 Floating-point constant 0.0
1
1 'A'
1 A 'lo_sum' data-linkage-table memory operand
1
1 'Q'
1 A memory operand that can be used as the destination operand
1 of an integer store instruction
1
1 'R'
1 A scaled or unscaled indexed memory operand
1
1 'T'
1 A memory operand for floating-point loads and stores
1
1 'W'
1 A register indirect memory operand
1
1 _Intel IA-64--'config/ia64/ia64.h'_
1 'a'
1 General register 'r0' to 'r3' for 'addl' instruction
1
1 'b'
1 Branch register
1
1 'c'
1 Predicate register ('c' as in "conditional")
1
1 'd'
1 Application register residing in M-unit
1
1 'e'
1 Application register residing in I-unit
1
1 'f'
1 Floating-point register
1
1 'm'
1 Memory operand. If used together with '<' or '>', the operand
1 can have postincrement and postdecrement which require
1 printing with '%Pn' on IA-64.
1
1 'G'
1 Floating-point constant 0.0 or 1.0
1
1 'I'
1 14-bit signed integer constant
1
1 'J'
1 22-bit signed integer constant
1
1 'K'
1 8-bit signed integer constant for logical instructions
1
1 'L'
1 8-bit adjusted signed integer constant for compare pseudo-ops
1
1 'M'
1 6-bit unsigned integer constant for shift counts
1
1 'N'
1 9-bit signed integer constant for load and store
1 postincrements
1
1 'O'
1 The constant zero
1
1 'P'
1 0 or -1 for 'dep' instruction
1
1 'Q'
1 Non-volatile memory for floating-point loads and stores
1
1 'R'
1 Integer constant in the range 1 to 4 for 'shladd' instruction
1
1 'S'
1 Memory operand except postincrement and postdecrement. This
1 is now roughly the same as 'm' when not used together with '<'
1 or '>'.
1
1 _M32C--'config/m32c/m32c.c'_
1 'Rsp'
1 'Rfb'
1 'Rsb'
1 '$sp', '$fb', '$sb'.
1
1 'Rcr'
1 Any control register, when they're 16 bits wide (nothing if
1 control registers are 24 bits wide)
1
1 'Rcl'
1 Any control register, when they're 24 bits wide.
1
1 'R0w'
1 'R1w'
1 'R2w'
1 'R3w'
1 $r0, $r1, $r2, $r3.
1
1 'R02'
1 $r0 or $r2, or $r2r0 for 32 bit values.
1
1 'R13'
1 $r1 or $r3, or $r3r1 for 32 bit values.
1
1 'Rdi'
1 A register that can hold a 64 bit value.
1
1 'Rhl'
1 $r0 or $r1 (registers with addressable high/low bytes)
1
1 'R23'
1 $r2 or $r3
1
1 'Raa'
1 Address registers
1
1 'Raw'
1 Address registers when they're 16 bits wide.
1
1 'Ral'
1 Address registers when they're 24 bits wide.
1
1 'Rqi'
1 Registers that can hold QI values.
1
1 'Rad'
1 Registers that can be used with displacements ($a0, $a1, $sb).
1
1 'Rsi'
1 Registers that can hold 32 bit values.
1
1 'Rhi'
1 Registers that can hold 16 bit values.
1
1 'Rhc'
1 Registers chat can hold 16 bit values, including all control
1 registers.
1
1 'Rra'
1 $r0 through R1, plus $a0 and $a1.
1
1 'Rfl'
1 The flags register.
1
1 'Rmm'
1 The memory-based pseudo-registers $mem0 through $mem15.
1
1 'Rpi'
1 Registers that can hold pointers (16 bit registers for r8c,
1 m16c; 24 bit registers for m32cm, m32c).
1
1 'Rpa'
1 Matches multiple registers in a PARALLEL to form a larger
1 register. Used to match function return values.
1
1 'Is3'
1 -8 ... 7
1
1 'IS1'
1 -128 ... 127
1
1 'IS2'
1 -32768 ... 32767
1
1 'IU2'
1 0 ... 65535
1
1 'In4'
1 -8 ... -1 or 1 ... 8
1
1 'In5'
1 -16 ... -1 or 1 ... 16
1
1 'In6'
1 -32 ... -1 or 1 ... 32
1
1 'IM2'
1 -65536 ... -1
1
1 'Ilb'
1 An 8 bit value with exactly one bit set.
1
1 'Ilw'
1 A 16 bit value with exactly one bit set.
1
1 'Sd'
1 The common src/dest memory addressing modes.
1
1 'Sa'
1 Memory addressed using $a0 or $a1.
1
1 'Si'
1 Memory addressed with immediate addresses.
1
1 'Ss'
1 Memory addressed using the stack pointer ($sp).
1
1 'Sf'
1 Memory addressed using the frame base register ($fb).
1
1 'Ss'
1 Memory addressed using the small base register ($sb).
1
1 'S1'
1 $r1h
1
1 _MicroBlaze--'config/microblaze/constraints.md'_
1 'd'
1 A general register ('r0' to 'r31').
1
1 'z'
1 A status register ('rmsr', '$fcc1' to '$fcc7').
1
1 _MIPS--'config/mips/constraints.md'_
1 'd'
1 A general-purpose register. This is equivalent to 'r' unless
1 generating MIPS16 code, in which case the MIPS16 register set
1 is used.
1
1 'f'
1 A floating-point register (if available).
1
1 'h'
1 Formerly the 'hi' register. This constraint is no longer
1 supported.
1
1 'l'
1 The 'lo' register. Use this register to store values that are
1 no bigger than a word.
1
1 'x'
1 The concatenated 'hi' and 'lo' registers. Use this register
1 to store doubleword values.
1
1 'c'
1 A register suitable for use in an indirect jump. This will
1 always be '$25' for '-mabicalls'.
1
1 'v'
1 Register '$3'. Do not use this constraint in new code; it is
1 retained only for compatibility with glibc.
1
1 'y'
1 Equivalent to 'r'; retained for backwards compatibility.
1
1 'z'
1 A floating-point condition code register.
1
1 'I'
1 A signed 16-bit constant (for arithmetic instructions).
1
1 'J'
1 Integer zero.
1
1 'K'
1 An unsigned 16-bit constant (for logic instructions).
1
1 'L'
1 A signed 32-bit constant in which the lower 16 bits are zero.
1 Such constants can be loaded using 'lui'.
1
1 'M'
1 A constant that cannot be loaded using 'lui', 'addiu' or
1 'ori'.
1
1 'N'
1 A constant in the range -65535 to -1 (inclusive).
1
1 'O'
1 A signed 15-bit constant.
1
1 'P'
1 A constant in the range 1 to 65535 (inclusive).
1
1 'G'
1 Floating-point zero.
1
1 'R'
1 An address that can be used in a non-macro load or store.
1
1 'ZC'
1 A memory operand whose address is formed by a base register
1 and offset that is suitable for use in instructions with the
1 same addressing mode as 'll' and 'sc'.
1
1 'ZD'
1 An address suitable for a 'prefetch' instruction, or for any
1 other instruction with the same addressing mode as 'prefetch'.
1
1 _Motorola 680x0--'config/m68k/constraints.md'_
1 'a'
1 Address register
1
1 'd'
1 Data register
1
1 'f'
1 68881 floating-point register, if available
1
1 'I'
1 Integer in the range 1 to 8
1
1 'J'
1 16-bit signed number
1
1 'K'
1 Signed number whose magnitude is greater than 0x80
1
1 'L'
1 Integer in the range -8 to -1
1
1 'M'
1 Signed number whose magnitude is greater than 0x100
1
1 'N'
1 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
1
1 'O'
1 16 (for rotate using swap)
1
1 'P'
1 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
1
1 'R'
1 Numbers that mov3q can handle
1
1 'G'
1 Floating point constant that is not a 68881 constant
1
1 'S'
1 Operands that satisfy 'm' when -mpcrel is in effect
1
1 'T'
1 Operands that satisfy 's' when -mpcrel is not in effect
1
1 'Q'
1 Address register indirect addressing mode
1
1 'U'
1 Register offset addressing
1
1 'W'
1 const_call_operand
1
1 'Cs'
1 symbol_ref or const
1
1 'Ci'
1 const_int
1
1 'C0'
1 const_int 0
1
1 'Cj'
1 Range of signed numbers that don't fit in 16 bits
1
1 'Cmvq'
1 Integers valid for mvq
1
1 'Capsw'
1 Integers valid for a moveq followed by a swap
1
1 'Cmvz'
1 Integers valid for mvz
1
1 'Cmvs'
1 Integers valid for mvs
1
1 'Ap'
1 push_operand
1
1 'Ac'
1 Non-register operands allowed in clr
1
1 _Moxie--'config/moxie/constraints.md'_
1 'A'
1 An absolute address
1
1 'B'
1 An offset address
1
1 'W'
1 A register indirect memory operand
1
1 'I'
1 A constant in the range of 0 to 255.
1
1 'N'
1 A constant in the range of 0 to -255.
1
1 _MSP430-'config/msp430/constraints.md'_
1
1 'R12'
1 Register R12.
1
1 'R13'
1 Register R13.
1
1 'K'
1 Integer constant 1.
1
1 'L'
1 Integer constant -1^20..1^19.
1
1 'M'
1 Integer constant 1-4.
1
1 'Ya'
1 Memory references which do not require an extended MOVX
1 instruction.
1
1 'Yl'
1 Memory reference, labels only.
1
1 'Ys'
1 Memory reference, stack only.
1
1 _NDS32--'config/nds32/constraints.md'_
1 'w'
1 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
1 'l'
1 LOW register class $r0 to $r7.
1 'd'
1 MIDDLE register class $r0 to $r11, $r16 to $r19.
1 'h'
1 HIGH register class $r12 to $r14, $r20 to $r31.
1 't'
1 Temporary assist register $ta (i.e. $r15).
1 'k'
1 Stack register $sp.
1 'Iu03'
1 Unsigned immediate 3-bit value.
1 'In03'
1 Negative immediate 3-bit value in the range of -7-0.
1 'Iu04'
1 Unsigned immediate 4-bit value.
1 'Is05'
1 Signed immediate 5-bit value.
1 'Iu05'
1 Unsigned immediate 5-bit value.
1 'In05'
1 Negative immediate 5-bit value in the range of -31-0.
1 'Ip05'
1 Unsigned immediate 5-bit value for movpi45 instruction with
1 range 16-47.
1 'Iu06'
1 Unsigned immediate 6-bit value constraint for addri36.sp
1 instruction.
1 'Iu08'
1 Unsigned immediate 8-bit value.
1 'Iu09'
1 Unsigned immediate 9-bit value.
1 'Is10'
1 Signed immediate 10-bit value.
1 'Is11'
1 Signed immediate 11-bit value.
1 'Is15'
1 Signed immediate 15-bit value.
1 'Iu15'
1 Unsigned immediate 15-bit value.
1 'Ic15'
1 A constant which is not in the range of imm15u but ok for bclr
1 instruction.
1 'Ie15'
1 A constant which is not in the range of imm15u but ok for bset
1 instruction.
1 'It15'
1 A constant which is not in the range of imm15u but ok for btgl
1 instruction.
1 'Ii15'
1 A constant whose compliment value is in the range of imm15u
1 and ok for bitci instruction.
1 'Is16'
1 Signed immediate 16-bit value.
1 'Is17'
1 Signed immediate 17-bit value.
1 'Is19'
1 Signed immediate 19-bit value.
1 'Is20'
1 Signed immediate 20-bit value.
1 'Ihig'
1 The immediate value that can be simply set high 20-bit.
1 'Izeb'
1 The immediate value 0xff.
1 'Izeh'
1 The immediate value 0xffff.
1 'Ixls'
1 The immediate value 0x01.
1 'Ix11'
1 The immediate value 0x7ff.
1 'Ibms'
1 The immediate value with power of 2.
1 'Ifex'
1 The immediate value with power of 2 minus 1.
1 'U33'
1 Memory constraint for 333 format.
1 'U45'
1 Memory constraint for 45 format.
1 'U37'
1 Memory constraint for 37 format.
1
1 _Nios II family--'config/nios2/constraints.md'_
1
1 'I'
1 Integer that is valid as an immediate operand in an
1 instruction taking a signed 16-bit number. Range -32768 to
1 32767.
1
1 'J'
1 Integer that is valid as an immediate operand in an
1 instruction taking an unsigned 16-bit number. Range 0 to
1 65535.
1
1 'K'
1 Integer that is valid as an immediate operand in an
1 instruction taking only the upper 16-bits of a 32-bit number.
1 Range 32-bit numbers with the lower 16-bits being 0.
1
1 'L'
1 Integer that is valid as an immediate operand for a shift
1 instruction. Range 0 to 31.
1
1 'M'
1 Integer that is valid as an immediate operand for only the
1 value 0. Can be used in conjunction with the format modifier
1 'z' to use 'r0' instead of '0' in the assembly output.
1
1 'N'
1 Integer that is valid as an immediate operand for a custom
1 instruction opcode. Range 0 to 255.
1
1 'P'
1 An immediate operand for R2 andchi/andci instructions.
1
1 'S'
1 Matches immediates which are addresses in the small data
1 section and therefore can be added to 'gp' as a 16-bit
1 immediate to re-create their 32-bit value.
1
1 'U'
1 Matches constants suitable as an operand for the rdprs and
1 cache instructions.
1
1 'v'
1 A memory operand suitable for Nios II R2 load/store exclusive
1 instructions.
1
1 'w'
1 A memory operand suitable for load/store IO and cache
1 instructions.
1
1 'T'
1 A 'const' wrapped 'UNSPEC' expression, representing a
1 supported PIC or TLS relocation.
1
1 _PDP-11--'config/pdp11/constraints.md'_
1 'a'
1 Floating point registers AC0 through AC3. These can be loaded
1 from/to memory with a single instruction.
1
1 'd'
1 Odd numbered general registers (R1, R3, R5). These are used
1 for 16-bit multiply operations.
1
1 'f'
1 Any of the floating point registers (AC0 through AC5).
1
1 'G'
1 Floating point constant 0.
1
1 'I'
1 An integer constant that fits in 16 bits.
1
1 'J'
1 An integer constant whose low order 16 bits are zero.
1
1 'K'
1 An integer constant that does not meet the constraints for
1 codes 'I' or 'J'.
1
1 'L'
1 The integer constant 1.
1
1 'M'
1 The integer constant -1.
1
1 'N'
1 The integer constant 0.
1
1 'O'
1 Integer constants -4 through -1 and 1 through 4; shifts by
1 these amounts are handled as multiple single-bit shifts rather
1 than a single variable-length shift.
1
1 'Q'
1 A memory reference which requires an additional word (address
1 or offset) after the opcode.
1
1 'R'
1 A memory reference that is encoded within the opcode.
1
1 _PowerPC and IBM RS6000--'config/rs6000/constraints.md'_
1 'b'
1 Address base register
1
1 'd'
1 Floating point register (containing 64-bit value)
1
1 'f'
1 Floating point register (containing 32-bit value)
1
1 'v'
1 Altivec vector register
1
1 'wa'
1 Any VSX register if the '-mvsx' option was used or NO_REGS.
1
1 When using any of the register constraints ('wa', 'wd', 'wf',
1 'wg', 'wh', 'wi', 'wj', 'wk', 'wl', 'wm', 'wo', 'wp', 'wq',
1 'ws', 'wt', 'wu', 'wv', 'ww', or 'wy') that take VSX
1 registers, you must use '%x<n>' in the template so that the
1 correct register is used. Otherwise the register number
1 output in the assembly file will be incorrect if an Altivec
1 register is an operand of a VSX instruction that expects VSX
1 register numbering.
1
1 asm ("xvadddp %x0,%x1,%x2"
1 : "=wa" (v1)
1 : "wa" (v2), "wa" (v3));
1
1 is correct, but:
1
1 asm ("xvadddp %0,%1,%2"
1 : "=wa" (v1)
1 : "wa" (v2), "wa" (v3));
1
1 is not correct.
1
1 If an instruction only takes Altivec registers, you do not
1 want to use '%x<n>'.
1
1 asm ("xsaddqp %0,%1,%2"
1 : "=v" (v1)
1 : "v" (v2), "v" (v3));
1
1 is correct because the 'xsaddqp' instruction only takes
1 Altivec registers, while:
1
1 asm ("xsaddqp %x0,%x1,%x2"
1 : "=v" (v1)
1 : "v" (v2), "v" (v3));
1
1 is incorrect.
1
1 'wb'
1 Altivec register if '-mcpu=power9' is used or NO_REGS.
1
1 'wd'
1 VSX vector register to hold vector double data or NO_REGS.
1
1 'we'
1 VSX register if the '-mcpu=power9' and '-m64' options were
1 used or NO_REGS.
1
1 'wf'
1 VSX vector register to hold vector float data or NO_REGS.
1
1 'wg'
1 If '-mmfpgpr' was used, a floating point register or NO_REGS.
1
1 'wh'
1 Floating point register if direct moves are available, or
1 NO_REGS.
1
1 'wi'
1 FP or VSX register to hold 64-bit integers for VSX insns or
1 NO_REGS.
1
1 'wj'
1 FP or VSX register to hold 64-bit integers for direct moves or
1 NO_REGS.
1
1 'wk'
1 FP or VSX register to hold 64-bit doubles for direct moves or
1 NO_REGS.
1
1 'wl'
1 Floating point register if the LFIWAX instruction is enabled
1 or NO_REGS.
1
1 'wm'
1 VSX register if direct move instructions are enabled, or
1 NO_REGS.
1
1 'wn'
1 No register (NO_REGS).
1
1 'wo'
1 VSX register to use for ISA 3.0 vector instructions, or
1 NO_REGS.
1
1 'wp'
1 VSX register to use for IEEE 128-bit floating point TFmode, or
1 NO_REGS.
1
1 'wq'
1 VSX register to use for IEEE 128-bit floating point, or
1 NO_REGS.
1
1 'wr'
1 General purpose register if 64-bit instructions are enabled or
1 NO_REGS.
1
1 'ws'
1 VSX vector register to hold scalar double values or NO_REGS.
1
1 'wt'
1 VSX vector register to hold 128 bit integer or NO_REGS.
1
1 'wu'
1 Altivec register to use for float/32-bit int loads/stores or
1 NO_REGS.
1
1 'wv'
1 Altivec register to use for double loads/stores or NO_REGS.
1
1 'ww'
1 FP or VSX register to perform float operations under '-mvsx'
1 or NO_REGS.
1
1 'wx'
1 Floating point register if the STFIWX instruction is enabled
1 or NO_REGS.
1
1 'wy'
1 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
1
1 'wz'
1 Floating point register if the LFIWZX instruction is enabled
1 or NO_REGS.
1
1 'wA'
1 Address base register if 64-bit instructions are enabled or
1 NO_REGS.
1
1 'wB'
1 Signed 5-bit constant integer that can be loaded into an
1 altivec register.
1
1 'wD'
1 Int constant that is the element number of the 64-bit scalar
1 in a vector.
1
1 'wE'
1 Vector constant that can be loaded with the XXSPLTIB
1 instruction.
1
1 'wF'
1 Memory operand suitable for power9 fusion load/stores.
1
1 'wG'
1 Memory operand suitable for TOC fusion memory references.
1
1 'wH'
1 Altivec register if '-mvsx-small-integer'.
1
1 'wI'
1 Floating point register if '-mvsx-small-integer'.
1
1 'wJ'
1 FP register if '-mvsx-small-integer' and '-mpower9-vector'.
1
1 'wK'
1 Altivec register if '-mvsx-small-integer' and
1 '-mpower9-vector'.
1
1 'wL'
1 Int constant that is the element number that the MFVSRLD
1 instruction. targets.
1
1 'wM'
1 Match vector constant with all 1's if the XXLORC instruction
1 is available.
1
1 'wO'
1 A memory operand suitable for the ISA 3.0 vector d-form
1 instructions.
1
1 'wQ'
1 A memory address that will work with the 'lq' and 'stq'
1 instructions.
1
1 'wS'
1 Vector constant that can be loaded with XXSPLTIB & sign
1 extension.
1
1 'h'
1 'MQ', 'CTR', or 'LINK' register
1
1 'c'
1 'CTR' register
1
1 'l'
1 'LINK' register
1
1 'x'
1 'CR' register (condition register) number 0
1
1 'y'
1 'CR' register (condition register)
1
1 'z'
1 'XER[CA]' carry bit (part of the XER register)
1
1 'I'
1 Signed 16-bit constant
1
1 'J'
1 Unsigned 16-bit constant shifted left 16 bits (use 'L' instead
1 for 'SImode' constants)
1
1 'K'
1 Unsigned 16-bit constant
1
1 'L'
1 Signed 16-bit constant shifted left 16 bits
1
1 'M'
1 Constant larger than 31
1
1 'N'
1 Exact power of 2
1
1 'O'
1 Zero
1
1 'P'
1 Constant whose negation is a signed 16-bit constant
1
1 'G'
1 Floating point constant that can be loaded into a register
1 with one instruction per word
1
1 'H'
1 Integer/Floating point constant that can be loaded into a
1 register using three instructions
1
1 'm'
1 Memory operand. Normally, 'm' does not allow addresses that
1 update the base register. If '<' or '>' constraint is also
1 used, they are allowed and therefore on PowerPC targets in
1 that case it is only safe to use 'm<>' in an 'asm' statement
1 if that 'asm' statement accesses the operand exactly once.
1 The 'asm' statement must also use '%U<OPNO>' as a placeholder
1 for the "update" flag in the corresponding load or store
1 instruction. For example:
1
1 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
1
1 is correct but:
1
1 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
1
1 is not.
1
1 'es'
1 A "stable" memory operand; that is, one which does not include
1 any automodification of the base register. This used to be
1 useful when 'm' allowed automodification of the base register,
1 but as those are now only allowed when '<' or '>' is used,
1 'es' is basically the same as 'm' without '<' and '>'.
1
1 'Q'
1 Memory operand that is an offset from a register (it is
1 usually better to use 'm' or 'es' in 'asm' statements)
1
1 'Z'
1 Memory operand that is an indexed or indirect from a register
1 (it is usually better to use 'm' or 'es' in 'asm' statements)
1
1 'R'
1 AIX TOC entry
1
1 'a'
1 Address operand that is an indexed or indirect from a register
1 ('p' is preferable for 'asm' statements)
1
1 'U'
1 System V Release 4 small data area reference
1
1 'W'
1 Vector constant that does not require memory
1
1 'j'
1 Vector constant that is all zeros.
1
1 _RL78--'config/rl78/constraints.md'_
1
1 'Int3'
1 An integer constant in the range 1 ... 7.
1 'Int8'
1 An integer constant in the range 0 ... 255.
1 'J'
1 An integer constant in the range -255 ... 0
1 'K'
1 The integer constant 1.
1 'L'
1 The integer constant -1.
1 'M'
1 The integer constant 0.
1 'N'
1 The integer constant 2.
1 'O'
1 The integer constant -2.
1 'P'
1 An integer constant in the range 1 ... 15.
1 'Qbi'
1 The built-in compare types-eq, ne, gtu, ltu, geu, and leu.
1 'Qsc'
1 The synthetic compare types-gt, lt, ge, and le.
1 'Wab'
1 A memory reference with an absolute address.
1 'Wbc'
1 A memory reference using 'BC' as a base register, with an
1 optional offset.
1 'Wca'
1 A memory reference using 'AX', 'BC', 'DE', or 'HL' for the
1 address, for calls.
1 'Wcv'
1 A memory reference using any 16-bit register pair for the
1 address, for calls.
1 'Wd2'
1 A memory reference using 'DE' as a base register, with an
1 optional offset.
1 'Wde'
1 A memory reference using 'DE' as a base register, without any
1 offset.
1 'Wfr'
1 Any memory reference to an address in the far address space.
1 'Wh1'
1 A memory reference using 'HL' as a base register, with an
1 optional one-byte offset.
1 'Whb'
1 A memory reference using 'HL' as a base register, with 'B' or
1 'C' as the index register.
1 'Whl'
1 A memory reference using 'HL' as a base register, without any
1 offset.
1 'Ws1'
1 A memory reference using 'SP' as a base register, with an
1 optional one-byte offset.
1 'Y'
1 Any memory reference to an address in the near address space.
1 'A'
1 The 'AX' register.
1 'B'
1 The 'BC' register.
1 'D'
1 The 'DE' register.
1 'R'
1 'A' through 'L' registers.
1 'S'
1 The 'SP' register.
1 'T'
1 The 'HL' register.
1 'Z08W'
1 The 16-bit 'R8' register.
1 'Z10W'
1 The 16-bit 'R10' register.
1 'Zint'
1 The registers reserved for interrupts ('R24' to 'R31').
1 'a'
1 The 'A' register.
1 'b'
1 The 'B' register.
1 'c'
1 The 'C' register.
1 'd'
1 The 'D' register.
1 'e'
1 The 'E' register.
1 'h'
1 The 'H' register.
1 'l'
1 The 'L' register.
1 'v'
1 The virtual registers.
1 'w'
1 The 'PSW' register.
1 'x'
1 The 'X' register.
1
1 _RISC-V--'config/riscv/constraints.md'_
1
1 'f'
1 A floating-point register (if available).
1
1 'I'
1 An I-type 12-bit signed immediate.
1
1 'J'
1 Integer zero.
1
1 'K'
1 A 5-bit unsigned immediate for CSR access instructions.
1
1 'A'
1 An address that is held in a general-purpose register.
1
1 _RX--'config/rx/constraints.md'_
1 'Q'
1 An address which does not involve register indirect addressing
1 or pre/post increment/decrement addressing.
1
1 'Symbol'
1 A symbol reference.
1
1 'Int08'
1 A constant in the range -256 to 255, inclusive.
1
1 'Sint08'
1 A constant in the range -128 to 127, inclusive.
1
1 'Sint16'
1 A constant in the range -32768 to 32767, inclusive.
1
1 'Sint24'
1 A constant in the range -8388608 to 8388607, inclusive.
1
1 'Uint04'
1 A constant in the range 0 to 15, inclusive.
1
1 _S/390 and zSeries--'config/s390/s390.h'_
1 'a'
1 Address register (general purpose register except r0)
1
1 'c'
1 Condition code register
1
1 'd'
1 Data register (arbitrary general purpose register)
1
1 'f'
1 Floating-point register
1
1 'I'
1 Unsigned 8-bit constant (0-255)
1
1 'J'
1 Unsigned 12-bit constant (0-4095)
1
1 'K'
1 Signed 16-bit constant (-32768-32767)
1
1 'L'
1 Value appropriate as displacement.
1 '(0..4095)'
1 for short displacement
1 '(-524288..524287)'
1 for long displacement
1
1 'M'
1 Constant integer with a value of 0x7fffffff.
1
1 'N'
1 Multiple letter constraint followed by 4 parameter letters.
1 '0..9:'
1 number of the part counting from most to least
1 significant
1 'H,Q:'
1 mode of the part
1 'D,S,H:'
1 mode of the containing operand
1 '0,F:'
1 value of the other parts (F--all bits set)
1 The constraint matches if the specified part of a constant has
1 a value different from its other parts.
1
1 'Q'
1 Memory reference without index register and with short
1 displacement.
1
1 'R'
1 Memory reference with index register and short displacement.
1
1 'S'
1 Memory reference without index register but with long
1 displacement.
1
1 'T'
1 Memory reference with index register and long displacement.
1
1 'U'
1 Pointer with short displacement.
1
1 'W'
1 Pointer with long displacement.
1
1 'Y'
1 Shift count operand.
1
1 _SPARC--'config/sparc/sparc.h'_
1 'f'
1 Floating-point register on the SPARC-V8 architecture and lower
1 floating-point register on the SPARC-V9 architecture.
1
1 'e'
1 Floating-point register. It is equivalent to 'f' on the
1 SPARC-V8 architecture and contains both lower and upper
1 floating-point registers on the SPARC-V9 architecture.
1
1 'c'
1 Floating-point condition code register.
1
1 'd'
1 Lower floating-point register. It is only valid on the
1 SPARC-V9 architecture when the Visual Instruction Set is
1 available.
1
1 'b'
1 Floating-point register. It is only valid on the SPARC-V9
1 architecture when the Visual Instruction Set is available.
1
1 'h'
1 64-bit global or out register for the SPARC-V8+ architecture.
1
1 'C'
1 The constant all-ones, for floating-point.
1
1 'A'
1 Signed 5-bit constant
1
1 'D'
1 A vector constant
1
1 'I'
1 Signed 13-bit constant
1
1 'J'
1 Zero
1
1 'K'
1 32-bit constant with the low 12 bits clear (a constant that
1 can be loaded with the 'sethi' instruction)
1
1 'L'
1 A constant in the range supported by 'movcc' instructions
1 (11-bit signed immediate)
1
1 'M'
1 A constant in the range supported by 'movrcc' instructions
1 (10-bit signed immediate)
1
1 'N'
1 Same as 'K', except that it verifies that bits that are not in
1 the lower 32-bit range are all zero. Must be used instead of
1 'K' for modes wider than 'SImode'
1
1 'O'
1 The constant 4096
1
1 'G'
1 Floating-point zero
1
1 'H'
1 Signed 13-bit constant, sign-extended to 32 or 64 bits
1
1 'P'
1 The constant -1
1
1 'Q'
1 Floating-point constant whose integral representation can be
1 moved into an integer register using a single sethi
1 instruction
1
1 'R'
1 Floating-point constant whose integral representation can be
1 moved into an integer register using a single mov instruction
1
1 'S'
1 Floating-point constant whose integral representation can be
1 moved into an integer register using a high/lo_sum instruction
1 sequence
1
1 'T'
1 Memory address aligned to an 8-byte boundary
1
1 'U'
1 Even register
1
1 'W'
1 Memory address for 'e' constraint registers
1
1 'w'
1 Memory address with only a base register
1
1 'Y'
1 Vector zero
1
1 _SPU--'config/spu/spu.h'_
1 'a'
1 An immediate which can be loaded with the il/ila/ilh/ilhu
1 instructions. const_int is treated as a 64 bit value.
1
1 'c'
1 An immediate for and/xor/or instructions. const_int is
1 treated as a 64 bit value.
1
1 'd'
1 An immediate for the 'iohl' instruction. const_int is treated
1 as a 64 bit value.
1
1 'f'
1 An immediate which can be loaded with 'fsmbi'.
1
1 'A'
1 An immediate which can be loaded with the il/ila/ilh/ilhu
1 instructions. const_int is treated as a 32 bit value.
1
1 'B'
1 An immediate for most arithmetic instructions. const_int is
1 treated as a 32 bit value.
1
1 'C'
1 An immediate for and/xor/or instructions. const_int is
1 treated as a 32 bit value.
1
1 'D'
1 An immediate for the 'iohl' instruction. const_int is treated
1 as a 32 bit value.
1
1 'I'
1 A constant in the range [-64, 63] for shift/rotate
1 instructions.
1
1 'J'
1 An unsigned 7-bit constant for conversion/nop/channel
1 instructions.
1
1 'K'
1 A signed 10-bit constant for most arithmetic instructions.
1
1 'M'
1 A signed 16 bit immediate for 'stop'.
1
1 'N'
1 An unsigned 16-bit constant for 'iohl' and 'fsmbi'.
1
1 'O'
1 An unsigned 7-bit constant whose 3 least significant bits are
1 0.
1
1 'P'
1 An unsigned 3-bit constant for 16-byte rotates and shifts
1
1 'R'
1 Call operand, reg, for indirect calls
1
1 'S'
1 Call operand, symbol, for relative calls.
1
1 'T'
1 Call operand, const_int, for absolute calls.
1
1 'U'
1 An immediate which can be loaded with the il/ila/ilh/ilhu
1 instructions. const_int is sign extended to 128 bit.
1
1 'W'
1 An immediate for shift and rotate instructions. const_int is
1 treated as a 32 bit value.
1
1 'Y'
1 An immediate for and/xor/or instructions. const_int is sign
1 extended as a 128 bit.
1
1 'Z'
1 An immediate for the 'iohl' instruction. const_int is sign
1 extended to 128 bit.
1
1 _TI C6X family--'config/c6x/constraints.md'_
1 'a'
1 Register file A (A0-A31).
1
1 'b'
1 Register file B (B0-B31).
1
1 'A'
1 Predicate registers in register file A (A0-A2 on C64X and
1 higher, A1 and A2 otherwise).
1
1 'B'
1 Predicate registers in register file B (B0-B2).
1
1 'C'
1 A call-used register in register file B (B0-B9, B16-B31).
1
1 'Da'
1 Register file A, excluding predicate registers (A3-A31, plus
1 A0 if not C64X or higher).
1
1 'Db'
1 Register file B, excluding predicate registers (B3-B31).
1
1 'Iu4'
1 Integer constant in the range 0 ... 15.
1
1 'Iu5'
1 Integer constant in the range 0 ... 31.
1
1 'In5'
1 Integer constant in the range -31 ... 0.
1
1 'Is5'
1 Integer constant in the range -16 ... 15.
1
1 'I5x'
1 Integer constant that can be the operand of an ADDA or a SUBA
1 insn.
1
1 'IuB'
1 Integer constant in the range 0 ... 65535.
1
1 'IsB'
1 Integer constant in the range -32768 ... 32767.
1
1 'IsC'
1 Integer constant in the range -2^{20} ... 2^{20} - 1.
1
1 'Jc'
1 Integer constant that is a valid mask for the clr instruction.
1
1 'Js'
1 Integer constant that is a valid mask for the set instruction.
1
1 'Q'
1 Memory location with A base register.
1
1 'R'
1 Memory location with B base register.
1
1 'S0'
1 On C64x+ targets, a GP-relative small data reference.
1
1 'S1'
1 Any kind of 'SYMBOL_REF', for use in a call address.
1
1 'Si'
1 Any kind of immediate operand, unless it matches the S0
1 constraint.
1
1 'T'
1 Memory location with B base register, but not using a long
1 offset.
1
1 'W'
1 A memory operand with an address that cannot be used in an
1 unaligned access.
1
1 'Z'
1 Register B14 (aka DP).
1
1 _TILE-Gx--'config/tilegx/constraints.md'_
1 'R00'
1 'R01'
1 'R02'
1 'R03'
1 'R04'
1 'R05'
1 'R06'
1 'R07'
1 'R08'
1 'R09'
1 'R10'
1 Each of these represents a register constraint for an
1 individual register, from r0 to r10.
1
1 'I'
1 Signed 8-bit integer constant.
1
1 'J'
1 Signed 16-bit integer constant.
1
1 'K'
1 Unsigned 16-bit integer constant.
1
1 'L'
1 Integer constant that fits in one signed byte when incremented
1 by one (-129 ... 126).
1
1 'm'
1 Memory operand. If used together with '<' or '>', the operand
1 can have postincrement which requires printing with '%In' and
1 '%in' on TILE-Gx. For example:
1
1 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
1
1 'M'
1 A bit mask suitable for the BFINS instruction.
1
1 'N'
1 Integer constant that is a byte tiled out eight times.
1
1 'O'
1 The integer zero constant.
1
1 'P'
1 Integer constant that is a sign-extended byte tiled out as
1 four shorts.
1
1 'Q'
1 Integer constant that fits in one signed byte when incremented
1 (-129 ... 126), but excluding -1.
1
1 'S'
1 Integer constant that has all 1 bits consecutive and starting
1 at bit 0.
1
1 'T'
1 A 16-bit fragment of a got, tls, or pc-relative reference.
1
1 'U'
1 Memory operand except postincrement. This is roughly the same
1 as 'm' when not used together with '<' or '>'.
1
1 'W'
1 An 8-element vector constant with identical elements.
1
1 'Y'
1 A 4-element vector constant with identical elements.
1
1 'Z0'
1 The integer constant 0xffffffff.
1
1 'Z1'
1 The integer constant 0xffffffff00000000.
1
1 _TILEPro--'config/tilepro/constraints.md'_
1 'R00'
1 'R01'
1 'R02'
1 'R03'
1 'R04'
1 'R05'
1 'R06'
1 'R07'
1 'R08'
1 'R09'
1 'R10'
1 Each of these represents a register constraint for an
1 individual register, from r0 to r10.
1
1 'I'
1 Signed 8-bit integer constant.
1
1 'J'
1 Signed 16-bit integer constant.
1
1 'K'
1 Nonzero integer constant with low 16 bits zero.
1
1 'L'
1 Integer constant that fits in one signed byte when incremented
1 by one (-129 ... 126).
1
1 'm'
1 Memory operand. If used together with '<' or '>', the operand
1 can have postincrement which requires printing with '%In' and
1 '%in' on TILEPro. For example:
1
1 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
1
1 'M'
1 A bit mask suitable for the MM instruction.
1
1 'N'
1 Integer constant that is a byte tiled out four times.
1
1 'O'
1 The integer zero constant.
1
1 'P'
1 Integer constant that is a sign-extended byte tiled out as two
1 shorts.
1
1 'Q'
1 Integer constant that fits in one signed byte when incremented
1 (-129 ... 126), but excluding -1.
1
1 'T'
1 A symbolic operand, or a 16-bit fragment of a got, tls, or
1 pc-relative reference.
1
1 'U'
1 Memory operand except postincrement. This is roughly the same
1 as 'm' when not used together with '<' or '>'.
1
1 'W'
1 A 4-element vector constant with identical elements.
1
1 'Y'
1 A 2-element vector constant with identical elements.
1
1 _Visium--'config/visium/constraints.md'_
1 'b'
1 EAM register 'mdb'
1
1 'c'
1 EAM register 'mdc'
1
1 'f'
1 Floating point register
1
1 'k'
1 Register for sibcall optimization
1
1 'l'
1 General register, but not 'r29', 'r30' and 'r31'
1
1 't'
1 Register 'r1'
1
1 'u'
1 Register 'r2'
1
1 'v'
1 Register 'r3'
1
1 'G'
1 Floating-point constant 0.0
1
1 'J'
1 Integer constant in the range 0 .. 65535 (16-bit immediate)
1
1 'K'
1 Integer constant in the range 1 .. 31 (5-bit immediate)
1
1 'L'
1 Integer constant in the range -65535 .. -1 (16-bit negative
1 immediate)
1
1 'M'
1 Integer constant -1
1
1 'O'
1 Integer constant 0
1
1 'P'
1 Integer constant 32
1
1 _x86 family--'config/i386/constraints.md'_
1 'R'
1 Legacy register--the eight integer registers available on all
1 i386 processors ('a', 'b', 'c', 'd', 'si', 'di', 'bp', 'sp').
1
1 'q'
1 Any register accessible as 'Rl'. In 32-bit mode, 'a', 'b',
1 'c', and 'd'; in 64-bit mode, any integer register.
1
1 'Q'
1 Any register accessible as 'Rh': 'a', 'b', 'c', and 'd'.
1
1 'l'
1 Any register that can be used as the index in a base+index
1 memory access: that is, any general register except the stack
1 pointer.
1
1 'a'
1 The 'a' register.
1
1 'b'
1 The 'b' register.
1
1 'c'
1 The 'c' register.
1
1 'd'
1 The 'd' register.
1
1 'S'
1 The 'si' register.
1
1 'D'
1 The 'di' register.
1
1 'A'
1 The 'a' and 'd' registers. This class is used for
1 instructions that return double word results in the 'ax:dx'
1 register pair. Single word values will be allocated either in
1 'ax' or 'dx'. For example on i386 the following implements
1 'rdtsc':
1
1 unsigned long long rdtsc (void)
1 {
1 unsigned long long tick;
1 __asm__ __volatile__("rdtsc":"=A"(tick));
1 return tick;
1 }
1
1 This is not correct on x86-64 as it would allocate tick in
1 either 'ax' or 'dx'. You have to use the following variant
1 instead:
1
1 unsigned long long rdtsc (void)
1 {
1 unsigned int tickl, tickh;
1 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
1 return ((unsigned long long)tickh << 32)|tickl;
1 }
1
1 'U'
1 The call-clobbered integer registers.
1
1 'f'
1 Any 80387 floating-point (stack) register.
1
1 't'
1 Top of 80387 floating-point stack ('%st(0)').
1
1 'u'
1 Second from top of 80387 floating-point stack ('%st(1)').
1
1 'Yk'
1 Any mask register that can be used as a predicate, i.e.
1 'k1-k7'.
1
1 'k'
1 Any mask register.
1
1 'y'
1 Any MMX register.
1
1 'x'
1 Any SSE register.
1
1 'v'
1 Any EVEX encodable SSE register ('%xmm0-%xmm31').
1
1 'w'
1 Any bound register.
1
1 'Yz'
1 First SSE register ('%xmm0').
1
1 'Yi'
1 Any SSE register, when SSE2 and inter-unit moves are enabled.
1
1 'Yj'
1 Any SSE register, when SSE2 and inter-unit moves from vector
1 registers are enabled.
1
1 'Ym'
1 Any MMX register, when inter-unit moves are enabled.
1
1 'Yn'
1 Any MMX register, when inter-unit moves from vector registers
1 are enabled.
1
1 'Yp'
1 Any integer register when 'TARGET_PARTIAL_REG_STALL' is
1 disabled.
1
1 'Ya'
1 Any integer register when zero extensions with 'AND' are
1 disabled.
1
1 'Yb'
1 Any register that can be used as the GOT base when calling
1 '___tls_get_addr': that is, any general register except 'a'
1 and 'sp' registers, for '-fno-plt' if linker supports it.
1 Otherwise, 'b' register.
1
1 'Yf'
1 Any x87 register when 80387 floating-point arithmetic is
1 enabled.
1
1 'Yr'
1 Lower SSE register when avoiding REX prefix and all SSE
1 registers otherwise.
1
1 'Yv'
1 For AVX512VL, any EVEX-encodable SSE register
1 ('%xmm0-%xmm31'), otherwise any SSE register.
1
1 'Yh'
1 Any EVEX-encodable SSE register, that has number factor of
1 four.
1
1 'Bf'
1 Flags register operand.
1
1 'Bg'
1 GOT memory operand.
1
1 'Bm'
1 Vector memory operand.
1
1 'Bc'
1 Constant memory operand.
1
1 'Bn'
1 Memory operand without REX prefix.
1
1 'Bs'
1 Sibcall memory operand.
1
1 'Bw'
1 Call memory operand.
1
1 'Bz'
1 Constant call address operand.
1
1 'BC'
1 SSE constant -1 operand.
1
1 'I'
1 Integer constant in the range 0 ... 31, for 32-bit shifts.
1
1 'J'
1 Integer constant in the range 0 ... 63, for 64-bit shifts.
1
1 'K'
1 Signed 8-bit integer constant.
1
1 'L'
1 '0xFF' or '0xFFFF', for andsi as a zero-extending move.
1
1 'M'
1 0, 1, 2, or 3 (shifts for the 'lea' instruction).
1
1 'N'
1 Unsigned 8-bit integer constant (for 'in' and 'out'
1 instructions).
1
1 'O'
1 Integer constant in the range 0 ... 127, for 128-bit shifts.
1
1 'G'
1 Standard 80387 floating point constant.
1
1 'C'
1 SSE constant zero operand.
1
1 'e'
1 32-bit signed integer constant, or a symbolic reference known
1 to fit that range (for immediate operands in sign-extending
1 x86-64 instructions).
1
1 'We'
1 32-bit signed integer constant, or a symbolic reference known
1 to fit that range (for sign-extending conversion operations
1 that require non-'VOIDmode' immediate operands).
1
1 'Wz'
1 32-bit unsigned integer constant, or a symbolic reference
1 known to fit that range (for zero-extending conversion
1 operations that require non-'VOIDmode' immediate operands).
1
1 'Wd'
1 128-bit integer constant where both the high and low 64-bit
1 word satisfy the 'e' constraint.
1
1 'Z'
1 32-bit unsigned integer constant, or a symbolic reference
1 known to fit that range (for immediate operands in
1 zero-extending x86-64 instructions).
1
1 'Tv'
1 VSIB address operand.
1
1 'Ts'
1 Address operand without segment register.
1
1 'Ti'
1 MPX address operand without index.
1
1 'Tb'
1 MPX address operand without base.
1
1 _Xstormy16--'config/stormy16/stormy16.h'_
1 'a'
1 Register r0.
1
1 'b'
1 Register r1.
1
1 'c'
1 Register r2.
1
1 'd'
1 Register r8.
1
1 'e'
1 Registers r0 through r7.
1
1 't'
1 Registers r0 and r1.
1
1 'y'
1 The carry register.
1
1 'z'
1 Registers r8 and r9.
1
1 'I'
1 A constant between 0 and 3 inclusive.
1
1 'J'
1 A constant that has exactly one bit set.
1
1 'K'
1 A constant that has exactly one bit clear.
1
1 'L'
1 A constant between 0 and 255 inclusive.
1
1 'M'
1 A constant between -255 and 0 inclusive.
1
1 'N'
1 A constant between -3 and 0 inclusive.
1
1 'O'
1 A constant between 1 and 4 inclusive.
1
1 'P'
1 A constant between -4 and -1 inclusive.
1
1 'Q'
1 A memory reference that is a stack push.
1
1 'R'
1 A memory reference that is a stack pop.
1
1 'S'
1 A memory reference that refers to a constant address of known
1 value.
1
1 'T'
1 The register indicated by Rx (not implemented yet).
1
1 'U'
1 A constant that is not between 2 and 15 inclusive.
1
1 'Z'
1 The constant 0.
1
1 _Xtensa--'config/xtensa/constraints.md'_
1 'a'
1 General-purpose 32-bit register
1
1 'b'
1 One-bit boolean register
1
1 'A'
1 MAC16 40-bit accumulator register
1
1 'I'
1 Signed 12-bit integer constant, for use in MOVI instructions
1
1 'J'
1 Signed 8-bit integer constant, for use in ADDI instructions
1
1 'K'
1 Integer constant valid for BccI instructions
1
1 'L'
1 Unsigned constant valid for BccUI instructions
1