gccint: Simple Constraints
1
1 17.8.1 Simple Constraints
1 -------------------------
1
1 The simplest kind of constraint is a string full of letters, each of
1 which describes one kind of operand that is permitted. Here are the
1 letters that are allowed:
1
1 whitespace
1 Whitespace characters are ignored and can be inserted at any
1 position except the first. This enables each alternative for
1 different operands to be visually aligned in the machine
1 description even if they have different number of constraints and
1 modifiers.
1
1 'm'
1 A memory operand is allowed, with any kind of address that the
1 machine supports in general. Note that the letter used for the
1 general memory constraint can be re-defined by a back end using the
1 'TARGET_MEM_CONSTRAINT' macro.
1
1 'o'
1 A memory operand is allowed, but only if the address is
1 "offsettable". This means that adding a small integer (actually,
1 the width in bytes of the operand, as determined by its machine
1 mode) may be added to the address and the result is also a valid
1 memory address.
1
1 For example, an address which is constant is offsettable; so is an
1 address that is the sum of a register and a constant (as long as a
1 slightly larger constant is also within the range of
1 address-offsets supported by the machine); but an autoincrement or
1 autodecrement address is not offsettable. More complicated
1 indirect/indexed addresses may or may not be offsettable depending
1 on the other addressing modes that the machine supports.
1
1 Note that in an output operand which can be matched by another
1 operand, the constraint letter 'o' is valid only when accompanied
1 by both '<' (if the target machine has predecrement addressing) and
1 '>' (if the target machine has preincrement addressing).
1
1 'V'
1 A memory operand that is not offsettable. In other words, anything
1 that would fit the 'm' constraint but not the 'o' constraint.
1
1 '<'
1 A memory operand with autodecrement addressing (either predecrement
1 or postdecrement) is allowed. In inline 'asm' this constraint is
1 only allowed if the operand is used exactly once in an instruction
1 that can handle the side effects. Not using an operand with '<' in
1 constraint string in the inline 'asm' pattern at all or using it in
1 multiple instructions isn't valid, because the side effects
1 wouldn't be performed or would be performed more than once.
1 Furthermore, on some targets the operand with '<' in constraint
1 string must be accompanied by special instruction suffixes like
1 '%U0' instruction suffix on PowerPC or '%P0' on IA-64.
1
1 '>'
1 A memory operand with autoincrement addressing (either preincrement
1 or postincrement) is allowed. In inline 'asm' the same
1 restrictions as for '<' apply.
1
1 'r'
1 A register operand is allowed provided that it is in a general
1 register.
1
1 'i'
1 An immediate integer operand (one with constant value) is allowed.
1 This includes symbolic constants whose values will be known only at
1 assembly time or later.
1
1 'n'
1 An immediate integer operand with a known numeric value is allowed.
1 Many systems cannot support assembly-time constants for operands
1 less than a word wide. Constraints for these operands should use
1 'n' rather than 'i'.
1
1 'I', 'J', 'K', ... 'P'
1 Other letters in the range 'I' through 'P' may be defined in a
1 machine-dependent fashion to permit immediate integer operands with
1 explicit integer values in specified ranges. For example, on the
1 68000, 'I' is defined to stand for the range of values 1 to 8.
1 This is the range permitted as a shift count in the shift
1 instructions.
1
1 'E'
1 An immediate floating operand (expression code 'const_double') is
1 allowed, but only if the target floating point format is the same
1 as that of the host machine (on which the compiler is running).
1
1 'F'
1 An immediate floating operand (expression code 'const_double' or
1 'const_vector') is allowed.
1
1 'G', 'H'
1 'G' and 'H' may be defined in a machine-dependent fashion to permit
1 immediate floating operands in particular ranges of values.
1
1 's'
1 An immediate integer operand whose value is not an explicit integer
1 is allowed.
1
1 This might appear strange; if an insn allows a constant operand
1 with a value not known at compile time, it certainly must allow any
1 known value. So why use 's' instead of 'i'? Sometimes it allows
1 better code to be generated.
1
1 For example, on the 68000 in a fullword instruction it is possible
1 to use an immediate operand; but if the immediate value is between
1 -128 and 127, better code results from loading the value into a
1 register and using the register. This is because the load into the
1 register can be done with a 'moveq' instruction. We arrange for
1 this to happen by defining the letter 'K' to mean "any integer
1 outside the range -128 to 127", and then specifying 'Ks' in the
1 operand constraints.
1
1 'g'
1 Any register, memory or immediate integer operand is allowed,
1 except for registers that are not general registers.
1
1 'X'
1 Any operand whatsoever is allowed, even if it does not satisfy
1 'general_operand'. This is normally used in the constraint of a
1 'match_scratch' when certain alternatives will not actually require
1 a scratch register.
1
1 '0', '1', '2', ... '9'
1 An operand that matches the specified operand number is allowed.
1 If a digit is used together with letters within the same
1 alternative, the digit should come last.
1
1 This number is allowed to be more than a single digit. If multiple
1 digits are encountered consecutively, they are interpreted as a
1 single decimal integer. There is scant chance for ambiguity, since
1 to-date it has never been desirable that '10' be interpreted as
1 matching either operand 1 _or_ operand 0. Should this be desired,
1 one can use multiple alternatives instead.
1
1 This is called a "matching constraint" and what it really means is
1 that the assembler has only a single operand that fills two roles
1 considered separate in the RTL insn. For example, an add insn has
1 two input operands and one output operand in the RTL, but on most
1 CISC machines an add instruction really has only two operands, one
1 of them an input-output operand:
1
1 addl #35,r12
1
1 Matching constraints are used in these circumstances. More
1 precisely, the two operands that match must include one input-only
1 operand and one output-only operand. Moreover, the digit must be a
1 smaller number than the number of the operand that uses it in the
1 constraint.
1
1 For operands to match in a particular case usually means that they
1 are identical-looking RTL expressions. But in a few special cases
1 specific kinds of dissimilarity are allowed. For example, '*x' as
1 an input operand will match '*x++' as an output operand. For
1 proper results in such cases, the output template should always use
1 the output-operand's number when printing the operand.
1
1 'p'
1 An operand that is a valid memory address is allowed. This is for
1 "load address" and "push address" instructions.
1
1 'p' in the constraint must be accompanied by 'address_operand' as
1 the predicate in the 'match_operand'. This predicate interprets
1 the mode specified in the 'match_operand' as the mode of the memory
1 reference for which the address would be valid.
1
1 OTHER-LETTERS
1 Other letters can be defined in machine-dependent fashion to stand
1 for particular classes of registers or other arbitrary operand
1 types. 'd', 'a' and 'f' are defined on the 68000/68020 to stand
1 for data, address and floating point registers.
1
1 In order to have valid assembler code, each operand must satisfy its
1 constraint. But a failure to do so does not prevent the pattern from
1 applying to an insn. Instead, it directs the compiler to modify the
1 code so that the constraint will be satisfied. Usually this is done by
1 copying an operand into a register.
1
1 Contrast, therefore, the two instruction patterns that follow:
1
1 (define_insn ""
1 [(set (match_operand:SI 0 "general_operand" "=r")
1 (plus:SI (match_dup 0)
1 (match_operand:SI 1 "general_operand" "r")))]
1 ""
1 "...")
1
1 which has two operands, one of which must appear in two places, and
1
1 (define_insn ""
1 [(set (match_operand:SI 0 "general_operand" "=r")
1 (plus:SI (match_operand:SI 1 "general_operand" "0")
1 (match_operand:SI 2 "general_operand" "r")))]
1 ""
1 "...")
1
1 which has three operands, two of which are required by a constraint to
1 be identical. If we are considering an insn of the form
1
1 (insn N PREV NEXT
1 (set (reg:SI 3)
1 (plus:SI (reg:SI 6) (reg:SI 109)))
1 ...)
1
1 the first pattern would not apply at all, because this insn does not
1 contain two identical subexpressions in the right place. The pattern
1 would say, "That does not look like an add instruction; try other
1 patterns". The second pattern would say, "Yes, that's an add
1 instruction, but there is something wrong with it". It would direct the
1 reload pass of the compiler to generate additional insns to make the
1 constraint true. The results might look like this:
1
1 (insn N2 PREV N
1 (set (reg:SI 3) (reg:SI 6))
1 ...)
1
1 (insn N N2 NEXT
1 (set (reg:SI 3)
1 (plus:SI (reg:SI 3) (reg:SI 109)))
1 ...)
1
1 It is up to you to make sure that each operand, in each pattern, has
1 constraints that can handle any RTL expression that could be present for
1 that operand. (When multiple alternatives are in use, each pattern
1 must, for each possible combination of operand expressions, have at
1 least one alternative which can handle that combination of operands.)
1 The constraints don't need to _allow_ any possible operand--when this is
1 the case, they do not constrain--but they must at least point the way to
1 reloading any possible operand so that it will fit.
1
1 * If the constraint accepts whatever operands the predicate permits,
1 there is no problem: reloading is never necessary for this operand.
1
1 For example, an operand whose constraints permit everything except
1 registers is safe provided its predicate rejects registers.
1
1 An operand whose predicate accepts only constant values is safe
1 provided its constraints include the letter 'i'. If any possible
1 constant value is accepted, then nothing less than 'i' will do; if
1 the predicate is more selective, then the constraints may also be
1 more selective.
1
1 * Any operand expression can be reloaded by copying it into a
1 register. So if an operand's constraints allow some kind of
1 register, it is certain to be safe. It need not permit all classes
1 of registers; the compiler knows how to copy a register into
1 another register of the proper class in order to make an
1 instruction valid.
1
1 * A nonoffsettable memory reference can be reloaded by copying the
1 address into a register. So if the constraint uses the letter 'o',
1 all memory references are taken care of.
1
1 * A constant operand can be reloaded by allocating space in memory to
1 hold it as preinitialized data. Then the memory reference can be
1 used in place of the constant. So if the constraint uses the
1 letters 'o' or 'm', constant operands are not a problem.
1
1 * If the constraint permits a constant and a pseudo register used in
1 an insn was not allocated to a hard register and is equivalent to a
1 constant, the register will be replaced with the constant. If the
1 predicate does not permit a constant and the insn is re-recognized
1 for some reason, the compiler will crash. Thus the predicate must
1 always recognize any objects allowed by the constraint.
1
1 If the operand's predicate can recognize registers, but the constraint
1 does not permit them, it can make the compiler crash. When this operand
1 happens to be a register, the reload pass will be stymied, because it
1 does not know how to copy a register temporarily into memory.
1
1 If the predicate accepts a unary operator, the constraint applies to
1 the operand. For example, the MIPS processor at ISA level 3 supports an
1 instruction which adds two registers in 'SImode' to produce a 'DImode'
1 result, but only if the registers are correctly sign extended. This
1 predicate for the input operands accepts a 'sign_extend' of an 'SImode'
1 register. Write the constraint to indicate the type of register that is
1 required for the operand of the 'sign_extend'.
1