gcc: SPU Options

1 
1 3.18.47 SPU Options
1 -------------------
1 
1 These '-m' options are supported on the SPU:
1 
1 '-mwarn-reloc'
1 '-merror-reloc'
1 
1      The loader for SPU does not handle dynamic relocations.  By
1      default, GCC gives an error when it generates code that requires a
1      dynamic relocation.  '-mno-error-reloc' disables the error,
1      '-mwarn-reloc' generates a warning instead.
1 
1 '-msafe-dma'
1 '-munsafe-dma'
1 
1      Instructions that initiate or test completion of DMA must not be
1      reordered with respect to loads and stores of the memory that is
1      being accessed.  With '-munsafe-dma' you must use the 'volatile'
1      keyword to protect memory accesses, but that can lead to
1      inefficient code in places where the memory is known to not change.
1      Rather than mark the memory as volatile, you can use '-msafe-dma'
1      to tell the compiler to treat the DMA instructions as potentially
1      affecting all memory.
1 
1 '-mbranch-hints'
1 
1      By default, GCC generates a branch hint instruction to avoid
1      pipeline stalls for always-taken or probably-taken branches.  A
1      hint is not generated closer than 8 instructions away from its
1      branch.  There is little reason to disable them, except for
1      debugging purposes, or to make an object a little bit smaller.
1 
1 '-msmall-mem'
1 '-mlarge-mem'
1 
1      By default, GCC generates code assuming that addresses are never
1      larger than 18 bits.  With '-mlarge-mem' code is generated that
1      assumes a full 32-bit address.
1 
1 '-mstdmain'
1 
1      By default, GCC links against startup code that assumes the
1      SPU-style main function interface (which has an unconventional
1      parameter list).  With '-mstdmain', GCC links your program against
1      startup code that assumes a C99-style interface to 'main',
1      including a local copy of 'argv' strings.
1 
1 '-mfixed-range=REGISTER-RANGE'
1      Generate code treating the given register range as fixed registers.
1      A fixed register is one that the register allocator cannot use.
1      This is useful when compiling kernel code.  A register range is
1      specified as two registers separated by a dash.  Multiple register
1      ranges can be specified separated by a comma.
1 
1 '-mea32'
1 '-mea64'
1      Compile code assuming that pointers to the PPU address space
1      accessed via the '__ea' named address space qualifier are either 32
1      or 64 bits wide.  The default is 32 bits.  As this is an
1      ABI-changing option, all object code in an executable must be
1      compiled with the same setting.
1 
1 '-maddress-space-conversion'
1 '-mno-address-space-conversion'
1      Allow/disallow treating the '__ea' address space as superset of the
1      generic address space.  This enables explicit type casts between
1      '__ea' and generic pointer as well as implicit conversions of
1      generic pointers to '__ea' pointers.  The default is to allow
1      address space pointer conversions.
1 
1 '-mcache-size=CACHE-SIZE'
1      This option controls the version of libgcc that the compiler links
1      to an executable and selects a software-managed cache for accessing
1      variables in the '__ea' address space with a particular cache size.
1      Possible options for CACHE-SIZE are '8', '16', '32', '64' and
1      '128'.  The default cache size is 64KB.
1 
1 '-matomic-updates'
1 '-mno-atomic-updates'
1      This option controls the version of libgcc that the compiler links
1      to an executable and selects whether atomic updates to the
1      software-managed cache of PPU-side variables are used.  If you use
1      atomic updates, changes to a PPU variable from SPU code using the
1      '__ea' named address space qualifier do not interfere with changes
1      to other PPU variables residing in the same cache line from PPU
1      code.  If you do not use atomic updates, such interference may
1      occur; however, writing back cache lines is more efficient.  The
1      default behavior is to use atomic updates.
1 
1 '-mdual-nops'
1 '-mdual-nops=N'
1      By default, GCC inserts NOPs to increase dual issue when it expects
1      it to increase performance.  N can be a value from 0 to 10.  A
1      smaller N inserts fewer NOPs.  10 is the default, 0 is the same as
1      '-mno-dual-nops'.  Disabled with '-Os'.
1 
1 '-mhint-max-nops=N'
1      Maximum number of NOPs to insert for a branch hint.  A branch hint
1      must be at least 8 instructions away from the branch it is
1      affecting.  GCC inserts up to N NOPs to enforce this, otherwise it
1      does not generate the branch hint.
1 
1 '-mhint-max-distance=N'
1      The encoding of the branch hint instruction limits the hint to be
1      within 256 instructions of the branch it is affecting.  By default,
1      GCC makes sure it is within 125.
1 
1 '-msafe-hints'
1      Work around a hardware bug that causes the SPU to stall
1      indefinitely.  By default, GCC inserts the 'hbrp' instruction to
1      make sure this stall won't happen.
1