gcc: SPARC Options
1
1 3.18.46 SPARC Options
1 ---------------------
1
1 These '-m' options are supported on the SPARC:
1
1 '-mno-app-regs'
1 '-mapp-regs'
1 Specify '-mapp-regs' to generate output using the global registers
1 2 through 4, which the SPARC SVR4 ABI reserves for applications.
1 Like the global register 1, each global register 2 through 4 is
1 then treated as an allocable register that is clobbered by function
1 calls. This is the default.
1
1 To be fully SVR4 ABI-compliant at the cost of some performance
1 loss, specify '-mno-app-regs'. You should compile libraries and
1 system software with this option.
1
1 '-mflat'
1 '-mno-flat'
1 With '-mflat', the compiler does not generate save/restore
1 instructions and uses a "flat" or single register window model.
1 This model is compatible with the regular register window model.
1 The local registers and the input registers (0-5) are still treated
1 as "call-saved" registers and are saved on the stack as needed.
1
1 With '-mno-flat' (the default), the compiler generates save/restore
1 instructions (except for leaf functions). This is the normal
1 operating mode.
1
1 '-mfpu'
1 '-mhard-float'
1 Generate output containing floating-point instructions. This is
1 the default.
1
1 '-mno-fpu'
1 '-msoft-float'
1 Generate output containing library calls for floating point.
1 *Warning:* the requisite libraries are not available for all SPARC
1 targets. Normally the facilities of the machine's usual C compiler
1 are used, but this cannot be done directly in cross-compilation.
1 You must make your own arrangements to provide suitable library
1 functions for cross-compilation. The embedded targets
1 'sparc-*-aout' and 'sparclite-*-*' do provide software
1 floating-point support.
1
1 '-msoft-float' changes the calling convention in the output file;
1 therefore, it is only useful if you compile _all_ of a program with
1 this option. In particular, you need to compile 'libgcc.a', the
1 library that comes with GCC, with '-msoft-float' in order for this
1 to work.
1
1 '-mhard-quad-float'
1 Generate output containing quad-word (long double) floating-point
1 instructions.
1
1 '-msoft-quad-float'
1 Generate output containing library calls for quad-word (long
1 double) floating-point instructions. The functions called are
1 those specified in the SPARC ABI. This is the default.
1
1 As of this writing, there are no SPARC implementations that have
1 hardware support for the quad-word floating-point instructions.
1 They all invoke a trap handler for one of these instructions, and
1 then the trap handler emulates the effect of the instruction.
1 Because of the trap handler overhead, this is much slower than
1 calling the ABI library routines. Thus the '-msoft-quad-float'
1 option is the default.
1
1 '-mno-unaligned-doubles'
1 '-munaligned-doubles'
1 Assume that doubles have 8-byte alignment. This is the default.
1
1 With '-munaligned-doubles', GCC assumes that doubles have 8-byte
1 alignment only if they are contained in another type, or if they
1 have an absolute address. Otherwise, it assumes they have 4-byte
1 alignment. Specifying this option avoids some rare compatibility
1 problems with code generated by other compilers. It is not the
1 default because it results in a performance loss, especially for
1 floating-point code.
1
1 '-muser-mode'
1 '-mno-user-mode'
1 Do not generate code that can only run in supervisor mode. This is
1 relevant only for the 'casa' instruction emitted for the LEON3
1 processor. This is the default.
1
1 '-mfaster-structs'
1 '-mno-faster-structs'
1 With '-mfaster-structs', the compiler assumes that structures
1 should have 8-byte alignment. This enables the use of pairs of
1 'ldd' and 'std' instructions for copies in structure assignment, in
1 place of twice as many 'ld' and 'st' pairs. However, the use of
1 this changed alignment directly violates the SPARC ABI. Thus, it's
1 intended only for use on targets where the developer acknowledges
1 that their resulting code is not directly in line with the rules of
1 the ABI.
1
1 '-mstd-struct-return'
1 '-mno-std-struct-return'
1 With '-mstd-struct-return', the compiler generates checking code in
1 functions returning structures or unions to detect size mismatches
1 between the two sides of function calls, as per the 32-bit ABI.
1
1 The default is '-mno-std-struct-return'. This option has no effect
1 in 64-bit mode.
1
1 '-mlra'
1 '-mno-lra'
1 Enable Local Register Allocation. This is the default for SPARC
1 since GCC 7 so '-mno-lra' needs to be passed to get old Reload.
1
1 '-mcpu=CPU_TYPE'
1 Set the instruction set, register set, and instruction scheduling
1 parameters for machine type CPU_TYPE. Supported values for
1 CPU_TYPE are 'v7', 'cypress', 'v8', 'supersparc', 'hypersparc',
1 'leon', 'leon3', 'leon3v7', 'sparclite', 'f930', 'f934',
1 'sparclite86x', 'sparclet', 'tsc701', 'v9', 'ultrasparc',
1 'ultrasparc3', 'niagara', 'niagara2', 'niagara3', 'niagara4',
1 'niagara7' and 'm8'.
1
1 Native Solaris and GNU/Linux toolchains also support the value
1 'native', which selects the best architecture option for the host
1 processor. '-mcpu=native' has no effect if GCC does not recognize
1 the processor.
1
1 Default instruction scheduling parameters are used for values that
1 select an architecture and not an implementation. These are 'v7',
1 'v8', 'sparclite', 'sparclet', 'v9'.
1
1 Here is a list of each supported architecture and their supported
1 implementations.
1
1 v7
1 cypress, leon3v7
1
1 v8
1 supersparc, hypersparc, leon, leon3
1
1 sparclite
1 f930, f934, sparclite86x
1
1 sparclet
1 tsc701
1
1 v9
1 ultrasparc, ultrasparc3, niagara, niagara2, niagara3,
1 niagara4, niagara7, m8
1
1 By default (unless configured otherwise), GCC generates code for
1 the V7 variant of the SPARC architecture. With '-mcpu=cypress',
1 the compiler additionally optimizes it for the Cypress CY7C602
1 chip, as used in the SPARCStation/SPARCServer 3xx series. This is
1 also appropriate for the older SPARCStation 1, 2, IPX etc.
1
1 With '-mcpu=v8', GCC generates code for the V8 variant of the SPARC
1 architecture. The only difference from V7 code is that the
1 compiler emits the integer multiply and integer divide instructions
1 which exist in SPARC-V8 but not in SPARC-V7. With
1 '-mcpu=supersparc', the compiler additionally optimizes it for the
1 SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000
1 series.
1
1 With '-mcpu=sparclite', GCC generates code for the SPARClite
1 variant of the SPARC architecture. This adds the integer multiply,
1 integer divide step and scan ('ffs') instructions which exist in
1 SPARClite but not in SPARC-V7. With '-mcpu=f930', the compiler
1 additionally optimizes it for the Fujitsu MB86930 chip, which is
1 the original SPARClite, with no FPU. With '-mcpu=f934', the
1 compiler additionally optimizes it for the Fujitsu MB86934 chip,
1 which is the more recent SPARClite with FPU.
1
1 With '-mcpu=sparclet', GCC generates code for the SPARClet variant
1 of the SPARC architecture. This adds the integer multiply,
1 multiply/accumulate, integer divide step and scan ('ffs')
1 instructions which exist in SPARClet but not in SPARC-V7. With
1 '-mcpu=tsc701', the compiler additionally optimizes it for the
1 TEMIC SPARClet chip.
1
1 With '-mcpu=v9', GCC generates code for the V9 variant of the SPARC
1 architecture. This adds 64-bit integer and floating-point move
1 instructions, 3 additional floating-point condition code registers
1 and conditional move instructions. With '-mcpu=ultrasparc', the
1 compiler additionally optimizes it for the Sun UltraSPARC I/II/IIi
1 chips. With '-mcpu=ultrasparc3', the compiler additionally
1 optimizes it for the Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+
1 chips. With '-mcpu=niagara', the compiler additionally optimizes
1 it for Sun UltraSPARC T1 chips. With '-mcpu=niagara2', the
1 compiler additionally optimizes it for Sun UltraSPARC T2 chips.
1 With '-mcpu=niagara3', the compiler additionally optimizes it for
1 Sun UltraSPARC T3 chips. With '-mcpu=niagara4', the compiler
1 additionally optimizes it for Sun UltraSPARC T4 chips. With
1 '-mcpu=niagara7', the compiler additionally optimizes it for Oracle
1 SPARC M7 chips. With '-mcpu=m8', the compiler additionally
1 optimizes it for Oracle M8 chips.
1
1 '-mtune=CPU_TYPE'
1 Set the instruction scheduling parameters for machine type
1 CPU_TYPE, but do not set the instruction set or register set that
1 the option '-mcpu=CPU_TYPE' does.
1
1 The same values for '-mcpu=CPU_TYPE' can be used for
1 '-mtune=CPU_TYPE', but the only useful values are those that select
1 a particular CPU implementation. Those are 'cypress',
1 'supersparc', 'hypersparc', 'leon', 'leon3', 'leon3v7', 'f930',
1 'f934', 'sparclite86x', 'tsc701', 'ultrasparc', 'ultrasparc3',
1 'niagara', 'niagara2', 'niagara3', 'niagara4', 'niagara7' and 'm8'.
1 With native Solaris and GNU/Linux toolchains, 'native' can also be
1 used.
1
1 '-mv8plus'
1 '-mno-v8plus'
1 With '-mv8plus', GCC generates code for the SPARC-V8+ ABI. The
1 difference from the V8 ABI is that the global and out registers are
1 considered 64 bits wide. This is enabled by default on Solaris in
1 32-bit mode for all SPARC-V9 processors.
1
1 '-mvis'
1 '-mno-vis'
1 With '-mvis', GCC generates code that takes advantage of the
1 UltraSPARC Visual Instruction Set extensions. The default is
1 '-mno-vis'.
1
1 '-mvis2'
1 '-mno-vis2'
1 With '-mvis2', GCC generates code that takes advantage of version
1 2.0 of the UltraSPARC Visual Instruction Set extensions. The
1 default is '-mvis2' when targeting a cpu that supports such
1 instructions, such as UltraSPARC-III and later. Setting '-mvis2'
1 also sets '-mvis'.
1
1 '-mvis3'
1 '-mno-vis3'
1 With '-mvis3', GCC generates code that takes advantage of version
1 3.0 of the UltraSPARC Visual Instruction Set extensions. The
1 default is '-mvis3' when targeting a cpu that supports such
1 instructions, such as niagara-3 and later. Setting '-mvis3' also
1 sets '-mvis2' and '-mvis'.
1
1 '-mvis4'
1 '-mno-vis4'
1 With '-mvis4', GCC generates code that takes advantage of version
1 4.0 of the UltraSPARC Visual Instruction Set extensions. The
1 default is '-mvis4' when targeting a cpu that supports such
1 instructions, such as niagara-7 and later. Setting '-mvis4' also
1 sets '-mvis3', '-mvis2' and '-mvis'.
1
1 '-mvis4b'
1 '-mno-vis4b'
1 With '-mvis4b', GCC generates code that takes advantage of version
1 4.0 of the UltraSPARC Visual Instruction Set extensions, plus the
1 additional VIS instructions introduced in the Oracle SPARC
1 Architecture 2017. The default is '-mvis4b' when targeting a cpu
1 that supports such instructions, such as m8 and later. Setting
1 '-mvis4b' also sets '-mvis4', '-mvis3', '-mvis2' and '-mvis'.
1
1 '-mcbcond'
1 '-mno-cbcond'
1 With '-mcbcond', GCC generates code that takes advantage of the
1 UltraSPARC Compare-and-Branch-on-Condition instructions. The
1 default is '-mcbcond' when targeting a CPU that supports such
1 instructions, such as Niagara-4 and later.
1
1 '-mfmaf'
1 '-mno-fmaf'
1 With '-mfmaf', GCC generates code that takes advantage of the
1 UltraSPARC Fused Multiply-Add Floating-point instructions. The
1 default is '-mfmaf' when targeting a CPU that supports such
1 instructions, such as Niagara-3 and later.
1
1 '-mfsmuld'
1 '-mno-fsmuld'
1 With '-mfsmuld', GCC generates code that takes advantage of the
1 Floating-point Multiply Single to Double (FsMULd) instruction. The
1 default is '-mfsmuld' when targeting a CPU supporting the
1 architecture versions V8 or V9 with FPU except '-mcpu=leon'.
1
1 '-mpopc'
1 '-mno-popc'
1 With '-mpopc', GCC generates code that takes advantage of the
1 UltraSPARC Population Count instruction. The default is '-mpopc'
1 when targeting a CPU that supports such an instruction, such as
1 Niagara-2 and later.
1
1 '-msubxc'
1 '-mno-subxc'
1 With '-msubxc', GCC generates code that takes advantage of the
1 UltraSPARC Subtract-Extended-with-Carry instruction. The default
1 is '-msubxc' when targeting a CPU that supports such an
1 instruction, such as Niagara-7 and later.
1
1 '-mfix-at697f'
1 Enable the documented workaround for the single erratum of the
1 Atmel AT697F processor (which corresponds to erratum #13 of the
1 AT697E processor).
1
1 '-mfix-ut699'
1 Enable the documented workarounds for the floating-point errata and
1 the data cache nullify errata of the UT699 processor.
1
1 '-mfix-ut700'
1 Enable the documented workaround for the back-to-back store errata
1 of the UT699E/UT700 processor.
1
1 '-mfix-gr712rc'
1 Enable the documented workaround for the back-to-back store errata
1 of the GR712RC processor.
1
1 These '-m' options are supported in addition to the above on SPARC-V9
1 processors in 64-bit environments:
1
1 '-m32'
1 '-m64'
1 Generate code for a 32-bit or 64-bit environment. The 32-bit
1 environment sets int, long and pointer to 32 bits. The 64-bit
1 environment sets int to 32 bits and long and pointer to 64 bits.
1
1 '-mcmodel=WHICH'
1 Set the code model to one of
1
1 'medlow'
1 The Medium/Low code model: 64-bit addresses, programs must be
1 linked in the low 32 bits of memory. Programs can be
1 statically or dynamically linked.
1
1 'medmid'
1 The Medium/Middle code model: 64-bit addresses, programs must
1 be linked in the low 44 bits of memory, the text and data
1 segments must be less than 2GB in size and the data segment
1 must be located within 2GB of the text segment.
1
1 'medany'
1 The Medium/Anywhere code model: 64-bit addresses, programs may
1 be linked anywhere in memory, the text and data segments must
1 be less than 2GB in size and the data segment must be located
1 within 2GB of the text segment.
1
1 'embmedany'
1 The Medium/Anywhere code model for embedded systems: 64-bit
1 addresses, the text and data segments must be less than 2GB in
1 size, both starting anywhere in memory (determined at link
1 time). The global register %g4 points to the base of the data
1 segment. Programs are statically linked and PIC is not
1 supported.
1
1 '-mmemory-model=MEM-MODEL'
1 Set the memory model in force on the processor to one of
1
1 'default'
1 The default memory model for the processor and operating
1 system.
1
1 'rmo'
1 Relaxed Memory Order
1
1 'pso'
1 Partial Store Order
1
1 'tso'
1 Total Store Order
1
1 'sc'
1 Sequential Consistency
1
1 These memory models are formally defined in Appendix D of the
1 SPARC-V9 architecture manual, as set in the processor's 'PSTATE.MM'
1 field.
1
1 '-mstack-bias'
1 '-mno-stack-bias'
1 With '-mstack-bias', GCC assumes that the stack pointer, and frame
1 pointer if present, are offset by -2047 which must be added back
1 when making stack frame references. This is the default in 64-bit
1 mode. Otherwise, assume no such offset is present.
1