gcc: PowerPC Function Attributes
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1 6.31.23 PowerPC Function Attributes
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1 These function attributes are supported by the PowerPC back end:
1
1 'longcall'
1 'shortcall'
1 The 'longcall' attribute indicates that the function might be far
1 away from the call site and require a different (more expensive)
1 calling sequence. The 'shortcall' attribute indicates that the
1 function is always close enough for the shorter calling sequence to
1 be used. These attributes override both the '-mlongcall' switch
1 and the '#pragma longcall' setting.
1
1 ⇒RS/6000 and PowerPC Options, for more information on
1 whether long calls are necessary.
1
1 'target (OPTIONS)'
1 As discussed in ⇒Common Function Attributes, this attribute
1 allows specification of target-specific compilation options.
1
1 On the PowerPC, the following options are allowed:
1
1 'altivec'
1 'no-altivec'
1 Generate code that uses (does not use) AltiVec instructions.
1 In 32-bit code, you cannot enable AltiVec instructions unless
1 '-mabi=altivec' is used on the command line.
1
1 'cmpb'
1 'no-cmpb'
1 Generate code that uses (does not use) the compare bytes
1 instruction implemented on the POWER6 processor and other
1 processors that support the PowerPC V2.05 architecture.
1
1 'dlmzb'
1 'no-dlmzb'
1 Generate code that uses (does not use) the string-search
1 'dlmzb' instruction on the IBM 405, 440, 464 and 476
1 processors. This instruction is generated by default when
1 targeting those processors.
1
1 'fprnd'
1 'no-fprnd'
1 Generate code that uses (does not use) the FP round to integer
1 instructions implemented on the POWER5+ processor and other
1 processors that support the PowerPC V2.03 architecture.
1
1 'hard-dfp'
1 'no-hard-dfp'
1 Generate code that uses (does not use) the decimal
1 floating-point instructions implemented on some POWER
1 processors.
1
1 'isel'
1 'no-isel'
1 Generate code that uses (does not use) ISEL instruction.
1
1 'mfcrf'
1 'no-mfcrf'
1 Generate code that uses (does not use) the move from condition
1 register field instruction implemented on the POWER4 processor
1 and other processors that support the PowerPC V2.01
1 architecture.
1
1 'mfpgpr'
1 'no-mfpgpr'
1 Generate code that uses (does not use) the FP move to/from
1 general purpose register instructions implemented on the
1 POWER6X processor and other processors that support the
1 extended PowerPC V2.05 architecture.
1
1 'mulhw'
1 'no-mulhw'
1 Generate code that uses (does not use) the half-word multiply
1 and multiply-accumulate instructions on the IBM 405, 440, 464
1 and 476 processors. These instructions are generated by
1 default when targeting those processors.
1
1 'multiple'
1 'no-multiple'
1 Generate code that uses (does not use) the load multiple word
1 instructions and the store multiple word instructions.
1
1 'update'
1 'no-update'
1 Generate code that uses (does not use) the load or store
1 instructions that update the base register to the address of
1 the calculated memory location.
1
1 'popcntb'
1 'no-popcntb'
1 Generate code that uses (does not use) the popcount and
1 double-precision FP reciprocal estimate instruction
1 implemented on the POWER5 processor and other processors that
1 support the PowerPC V2.02 architecture.
1
1 'popcntd'
1 'no-popcntd'
1 Generate code that uses (does not use) the popcount
1 instruction implemented on the POWER7 processor and other
1 processors that support the PowerPC V2.06 architecture.
1
1 'powerpc-gfxopt'
1 'no-powerpc-gfxopt'
1 Generate code that uses (does not use) the optional PowerPC
1 architecture instructions in the Graphics group, including
1 floating-point select.
1
1 'powerpc-gpopt'
1 'no-powerpc-gpopt'
1 Generate code that uses (does not use) the optional PowerPC
1 architecture instructions in the General Purpose group,
1 including floating-point square root.
1
1 'recip-precision'
1 'no-recip-precision'
1 Assume (do not assume) that the reciprocal estimate
1 instructions provide higher-precision estimates than is
1 mandated by the PowerPC ABI.
1
1 'string'
1 'no-string'
1 Generate code that uses (does not use) the load string
1 instructions and the store string word instructions to save
1 multiple registers and do small block moves.
1
1 'vsx'
1 'no-vsx'
1 Generate code that uses (does not use) vector/scalar (VSX)
1 instructions, and also enable the use of built-in functions
1 that allow more direct access to the VSX instruction set. In
1 32-bit code, you cannot enable VSX or AltiVec instructions
1 unless '-mabi=altivec' is used on the command line.
1
1 'friz'
1 'no-friz'
1 Generate (do not generate) the 'friz' instruction when the
1 '-funsafe-math-optimizations' option is used to optimize
1 rounding a floating-point value to 64-bit integer and back to
1 floating point. The 'friz' instruction does not return the
1 same value if the floating-point number is too large to fit in
1 an integer.
1
1 'avoid-indexed-addresses'
1 'no-avoid-indexed-addresses'
1 Generate code that tries to avoid (not avoid) the use of
1 indexed load or store instructions.
1
1 'paired'
1 'no-paired'
1 Generate code that uses (does not use) the generation of
1 PAIRED simd instructions.
1
1 'longcall'
1 'no-longcall'
1 Generate code that assumes (does not assume) that all calls
1 are far away so that a longer more expensive calling sequence
1 is required.
1
1 'cpu=CPU'
1 Specify the architecture to generate code for when compiling
1 the function. If you select the 'target("cpu=power7")'
1 attribute when generating 32-bit code, VSX and AltiVec
1 instructions are not generated unless you use the
1 '-mabi=altivec' option on the command line.
1
1 'tune=TUNE'
1 Specify the architecture to tune for when compiling the
1 function. If you do not specify the 'target("tune=TUNE")'
1 attribute and you do specify the 'target("cpu=CPU")'
1 attribute, compilation tunes for the CPU architecture, and not
1 the default tuning specified on the command line.
1
1 On the PowerPC, the inliner does not inline a function that has
1 different target options than the caller, unless the callee has a
1 subset of the target options of the caller.
1