gcc: RS/6000 and PowerPC Options
1
1 3.18.40 IBM RS/6000 and PowerPC Options
1 ---------------------------------------
1
1 These '-m' options are defined for the IBM RS/6000 and PowerPC:
1 '-mpowerpc-gpopt'
1 '-mno-powerpc-gpopt'
1 '-mpowerpc-gfxopt'
1 '-mno-powerpc-gfxopt'
1 '-mpowerpc64'
1 '-mno-powerpc64'
1 '-mmfcrf'
1 '-mno-mfcrf'
1 '-mpopcntb'
1 '-mno-popcntb'
1 '-mpopcntd'
1 '-mno-popcntd'
1 '-mfprnd'
1 '-mno-fprnd'
1 '-mcmpb'
1 '-mno-cmpb'
1 '-mmfpgpr'
1 '-mno-mfpgpr'
1 '-mhard-dfp'
1 '-mno-hard-dfp'
1 You use these options to specify which instructions are available
1 on the processor you are using. The default value of these options
1 is determined when configuring GCC. Specifying the
1 '-mcpu=CPU_TYPE' overrides the specification of these options. We
1 recommend you use the '-mcpu=CPU_TYPE' option rather than the
1 options listed above.
1
1 Specifying '-mpowerpc-gpopt' allows GCC to use the optional PowerPC
1 architecture instructions in the General Purpose group, including
1 floating-point square root. Specifying '-mpowerpc-gfxopt' allows
1 GCC to use the optional PowerPC architecture instructions in the
1 Graphics group, including floating-point select.
1
1 The '-mmfcrf' option allows GCC to generate the move from condition
1 register field instruction implemented on the POWER4 processor and
1 other processors that support the PowerPC V2.01 architecture. The
1 '-mpopcntb' option allows GCC to generate the popcount and
1 double-precision FP reciprocal estimate instruction implemented on
1 the POWER5 processor and other processors that support the PowerPC
1 V2.02 architecture. The '-mpopcntd' option allows GCC to generate
1 the popcount instruction implemented on the POWER7 processor and
1 other processors that support the PowerPC V2.06 architecture. The
1 '-mfprnd' option allows GCC to generate the FP round to integer
1 instructions implemented on the POWER5+ processor and other
1 processors that support the PowerPC V2.03 architecture. The
1 '-mcmpb' option allows GCC to generate the compare bytes
1 instruction implemented on the POWER6 processor and other
1 processors that support the PowerPC V2.05 architecture. The
1 '-mmfpgpr' option allows GCC to generate the FP move to/from
1 general-purpose register instructions implemented on the POWER6X
1 processor and other processors that support the extended PowerPC
1 V2.05 architecture. The '-mhard-dfp' option allows GCC to generate
1 the decimal floating-point instructions implemented on some POWER
1 processors.
1
1 The '-mpowerpc64' option allows GCC to generate the additional
1 64-bit instructions that are found in the full PowerPC64
1 architecture and to treat GPRs as 64-bit, doubleword quantities.
1 GCC defaults to '-mno-powerpc64'.
1
1 '-mcpu=CPU_TYPE'
1 Set architecture type, register usage, and instruction scheduling
1 parameters for machine type CPU_TYPE. Supported values for
1 CPU_TYPE are '401', '403', '405', '405fp', '440', '440fp', '464',
1 '464fp', '476', '476fp', '505', '601', '602', '603', '603e', '604',
1 '604e', '620', '630', '740', '7400', '7450', '750', '801', '821',
1 '823', '860', '970', '8540', 'a2', 'e300c2', 'e300c3', 'e500mc',
1 'e500mc64', 'e5500', 'e6500', 'ec603e', 'G3', 'G4', 'G5', 'titan',
1 'power3', 'power4', 'power5', 'power5+', 'power6', 'power6x',
1 'power7', 'power8', 'power9', 'powerpc', 'powerpc64',
1 'powerpc64le', 'rs64', and 'native'.
1
1 '-mcpu=powerpc', '-mcpu=powerpc64', and '-mcpu=powerpc64le' specify
1 pure 32-bit PowerPC (either endian), 64-bit big endian PowerPC and
1 64-bit little endian PowerPC architecture machine types, with an
1 appropriate, generic processor model assumed for scheduling
1 purposes.
1
1 Specifying 'native' as cpu type detects and selects the
1 architecture option that corresponds to the host processor of the
1 system performing the compilation. '-mcpu=native' has no effect if
1 GCC does not recognize the processor.
1
1 The other options specify a specific processor. Code generated
1 under those options runs best on that processor, and may not run at
1 all on others.
1
1 The '-mcpu' options automatically enable or disable the following
1 options:
1
1 -maltivec -mfprnd -mhard-float -mmfcrf -mmultiple
1 -mpopcntb -mpopcntd -mpowerpc64
1 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float
1 -msimple-fpu -mmulhw -mdlmzb -mmfpgpr -mvsx
1 -mcrypto -mhtm -mpower8-fusion -mpower8-vector
1 -mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware
1
1 The particular options set for any particular CPU varies between
1 compiler versions, depending on what setting seems to produce
1 optimal code for that CPU; it doesn't necessarily reflect the
1 actual hardware's capabilities. If you wish to set an individual
1 option to a particular value, you may specify it after the '-mcpu'
1 option, like '-mcpu=970 -mno-altivec'.
1
1 On AIX, the '-maltivec' and '-mpowerpc64' options are not enabled
1 or disabled by the '-mcpu' option at present because AIX does not
1 have full support for these options. You may still enable or
1 disable them individually if you're sure it'll work in your
1 environment.
1
1 '-mtune=CPU_TYPE'
1 Set the instruction scheduling parameters for machine type
1 CPU_TYPE, but do not set the architecture type or register usage,
1 as '-mcpu=CPU_TYPE' does. The same values for CPU_TYPE are used
1 for '-mtune' as for '-mcpu'. If both are specified, the code
1 generated uses the architecture and registers set by '-mcpu', but
1 the scheduling parameters set by '-mtune'.
1
1 '-mcmodel=small'
1 Generate PowerPC64 code for the small model: The TOC is limited to
1 64k.
1
1 '-mcmodel=medium'
1 Generate PowerPC64 code for the medium model: The TOC and other
1 static data may be up to a total of 4G in size. This is the
1 default for 64-bit Linux.
1
1 '-mcmodel=large'
1 Generate PowerPC64 code for the large model: The TOC may be up to
1 4G in size. Other data and code is only limited by the 64-bit
1 address space.
1
1 '-maltivec'
1 '-mno-altivec'
1 Generate code that uses (does not use) AltiVec instructions, and
1 also enable the use of built-in functions that allow more direct
1 access to the AltiVec instruction set. You may also need to set
1 '-mabi=altivec' to adjust the current ABI with AltiVec ABI
1 enhancements.
1
1 When '-maltivec' is used, rather than '-maltivec=le' or
1 '-maltivec=be', the element order for AltiVec intrinsics such as
1 'vec_splat', 'vec_extract', and 'vec_insert' match array element
1 order corresponding to the endianness of the target. That is,
1 element zero identifies the leftmost element in a vector register
1 when targeting a big-endian platform, and identifies the rightmost
1 element in a vector register when targeting a little-endian
1 platform.
1
1 '-maltivec=be'
1 Generate AltiVec instructions using big-endian element order,
1 regardless of whether the target is big- or little-endian. This is
1 the default when targeting a big-endian platform. Using this
1 option is currently deprecated. Support for this feature will be
1 removed in GCC 9.
1
1 The element order is used to interpret element numbers in AltiVec
1 intrinsics such as 'vec_splat', 'vec_extract', and 'vec_insert'.
1 By default, these match array element order corresponding to the
1 endianness for the target.
1
1 '-maltivec=le'
1 Generate AltiVec instructions using little-endian element order,
1 regardless of whether the target is big- or little-endian. This is
1 the default when targeting a little-endian platform. This option
1 is currently ignored when targeting a big-endian platform.
1
1 The element order is used to interpret element numbers in AltiVec
1 intrinsics such as 'vec_splat', 'vec_extract', and 'vec_insert'.
1 By default, these match array element order corresponding to the
1 endianness for the target.
1
1 '-mvrsave'
1 '-mno-vrsave'
1 Generate VRSAVE instructions when generating AltiVec code.
1
1 '-msecure-plt'
1 Generate code that allows 'ld' and 'ld.so' to build executables and
1 shared libraries with non-executable '.plt' and '.got' sections.
1 This is a PowerPC 32-bit SYSV ABI option.
1
1 '-mbss-plt'
1 Generate code that uses a BSS '.plt' section that 'ld.so' fills in,
1 and requires '.plt' and '.got' sections that are both writable and
1 executable. This is a PowerPC 32-bit SYSV ABI option.
1
1 '-misel'
1 '-mno-isel'
1 This switch enables or disables the generation of ISEL
1 instructions.
1
1 '-misel=YES/NO'
1 This switch has been deprecated. Use '-misel' and '-mno-isel'
1 instead.
1
1 '-mpaired'
1 '-mno-paired'
1 This switch enables or disables the generation of PAIRED simd
1 instructions.
1
1 '-mvsx'
1 '-mno-vsx'
1 Generate code that uses (does not use) vector/scalar (VSX)
1 instructions, and also enable the use of built-in functions that
1 allow more direct access to the VSX instruction set.
1
1 '-mcrypto'
1 '-mno-crypto'
1 Enable the use (disable) of the built-in functions that allow
1 direct access to the cryptographic instructions that were added in
1 version 2.07 of the PowerPC ISA.
1
1 '-mhtm'
1 '-mno-htm'
1 Enable (disable) the use of the built-in functions that allow
1 direct access to the Hardware Transactional Memory (HTM)
1 instructions that were added in version 2.07 of the PowerPC ISA.
1
1 '-mpower8-fusion'
1 '-mno-power8-fusion'
1 Generate code that keeps (does not keeps) some integer operations
1 adjacent so that the instructions can be fused together on power8
1 and later processors.
1
1 '-mpower8-vector'
1 '-mno-power8-vector'
1 Generate code that uses (does not use) the vector and scalar
1 instructions that were added in version 2.07 of the PowerPC ISA.
1 Also enable the use of built-in functions that allow more direct
1 access to the vector instructions.
1
1 '-mquad-memory'
1 '-mno-quad-memory'
1 Generate code that uses (does not use) the non-atomic quad word
1 memory instructions. The '-mquad-memory' option requires use of
1 64-bit mode.
1
1 '-mquad-memory-atomic'
1 '-mno-quad-memory-atomic'
1 Generate code that uses (does not use) the atomic quad word memory
1 instructions. The '-mquad-memory-atomic' option requires use of
1 64-bit mode.
1
1 '-mfloat128'
1 '-mno-float128'
1 Enable/disable the __FLOAT128 keyword for IEEE 128-bit floating
1 point and use either software emulation for IEEE 128-bit floating
1 point or hardware instructions.
1
1 The VSX instruction set ('-mvsx', '-mcpu=power7', '-mcpu=power8'),
1 or '-mcpu=power9' must be enabled to use the IEEE 128-bit floating
1 point support. The IEEE 128-bit floating point support only works
1 on PowerPC Linux systems.
1
1 The default for '-mfloat128' is enabled on PowerPC Linux systems
1 using the VSX instruction set, and disabled on other systems.
1
1 If you use the ISA 3.0 instruction set ('-mpower9-vector' or
1 '-mcpu=power9') on a 64-bit system, the IEEE 128-bit floating point
1 support will also enable the generation of ISA 3.0 IEEE 128-bit
1 floating point instructions. Otherwise, if you do not specify to
1 generate ISA 3.0 instructions or you are targeting a 32-bit big
1 endian system, IEEE 128-bit floating point will be done with
1 software emulation.
1
1 '-mfloat128-hardware'
1 '-mno-float128-hardware'
1 Enable/disable using ISA 3.0 hardware instructions to support the
1 __FLOAT128 data type.
1
1 The default for '-mfloat128-hardware' is enabled on PowerPC Linux
1 systems using the ISA 3.0 instruction set, and disabled on other
1 systems.
1
1 '-m32'
1 '-m64'
1 Generate code for 32-bit or 64-bit environments of Darwin and SVR4
1 targets (including GNU/Linux). The 32-bit environment sets int,
1 long and pointer to 32 bits and generates code that runs on any
1 PowerPC variant. The 64-bit environment sets int to 32 bits and
1 long and pointer to 64 bits, and generates code for PowerPC64, as
1 for '-mpowerpc64'.
1
1 '-mfull-toc'
1 '-mno-fp-in-toc'
1 '-mno-sum-in-toc'
1 '-mminimal-toc'
1 Modify generation of the TOC (Table Of Contents), which is created
1 for every executable file. The '-mfull-toc' option is selected by
1 default. In that case, GCC allocates at least one TOC entry for
1 each unique non-automatic variable reference in your program. GCC
1 also places floating-point constants in the TOC. However, only
1 16,384 entries are available in the TOC.
1
1 If you receive a linker error message that saying you have
1 overflowed the available TOC space, you can reduce the amount of
1 TOC space used with the '-mno-fp-in-toc' and '-mno-sum-in-toc'
1 options. '-mno-fp-in-toc' prevents GCC from putting floating-point
1 constants in the TOC and '-mno-sum-in-toc' forces GCC to generate
1 code to calculate the sum of an address and a constant at run time
1 instead of putting that sum into the TOC. You may specify one or
1 both of these options. Each causes GCC to produce very slightly
1 slower and larger code at the expense of conserving TOC space.
1
1 If you still run out of space in the TOC even when you specify both
1 of these options, specify '-mminimal-toc' instead. This option
1 causes GCC to make only one TOC entry for every file. When you
1 specify this option, GCC produces code that is slower and larger
1 but which uses extremely little TOC space. You may wish to use
1 this option only on files that contain less frequently-executed
1 code.
1
1 '-maix64'
1 '-maix32'
1 Enable 64-bit AIX ABI and calling convention: 64-bit pointers,
1 64-bit 'long' type, and the infrastructure needed to support them.
1 Specifying '-maix64' implies '-mpowerpc64', while '-maix32'
1 disables the 64-bit ABI and implies '-mno-powerpc64'. GCC defaults
1 to '-maix32'.
1
1 '-mxl-compat'
1 '-mno-xl-compat'
1 Produce code that conforms more closely to IBM XL compiler
1 semantics when using AIX-compatible ABI. Pass floating-point
1 arguments to prototyped functions beyond the register save area
1 (RSA) on the stack in addition to argument FPRs. Do not assume
1 that most significant double in 128-bit long double value is
1 properly rounded when comparing values and converting to double.
1 Use XL symbol names for long double support routines.
1
1 The AIX calling convention was extended but not initially
1 documented to handle an obscure K&R C case of calling a function
1 that takes the address of its arguments with fewer arguments than
1 declared. IBM XL compilers access floating-point arguments that do
1 not fit in the RSA from the stack when a subroutine is compiled
1 without optimization. Because always storing floating-point
1 arguments on the stack is inefficient and rarely needed, this
1 option is not enabled by default and only is necessary when calling
1 subroutines compiled by IBM XL compilers without optimization.
1
1 '-mpe'
1 Support "IBM RS/6000 SP" "Parallel Environment" (PE). Link an
1 application written to use message passing with special startup
1 code to enable the application to run. The system must have PE
1 installed in the standard location ('/usr/lpp/ppe.poe/'), or the
1 'specs' file must be overridden with the '-specs=' option to
1 specify the appropriate directory location. The Parallel
1 Environment does not support threads, so the '-mpe' option and the
1 '-pthread' option are incompatible.
1
1 '-malign-natural'
1 '-malign-power'
1 On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option
1 '-malign-natural' overrides the ABI-defined alignment of larger
1 types, such as floating-point doubles, on their natural size-based
1 boundary. The option '-malign-power' instructs GCC to follow the
1 ABI-specified alignment rules. GCC defaults to the standard
1 alignment defined in the ABI.
1
1 On 64-bit Darwin, natural alignment is the default, and
1 '-malign-power' is not supported.
1
1 '-msoft-float'
1 '-mhard-float'
1 Generate code that does not use (uses) the floating-point register
1 set. Software floating-point emulation is provided if you use the
1 '-msoft-float' option, and pass the option to GCC when linking.
1
1 '-msingle-float'
1 '-mdouble-float'
1 Generate code for single- or double-precision floating-point
1 operations. '-mdouble-float' implies '-msingle-float'.
1
1 '-msimple-fpu'
1 Do not generate 'sqrt' and 'div' instructions for hardware
1 floating-point unit.
1
1 '-mfpu=NAME'
1 Specify type of floating-point unit. Valid values for NAME are
1 'sp_lite' (equivalent to '-msingle-float -msimple-fpu'), 'dp_lite'
1 (equivalent to '-mdouble-float -msimple-fpu'), 'sp_full'
1 (equivalent to '-msingle-float'), and 'dp_full' (equivalent to
1 '-mdouble-float').
1
1 '-mxilinx-fpu'
1 Perform optimizations for the floating-point unit on Xilinx PPC
1 405/440.
1
1 '-mmultiple'
1 '-mno-multiple'
1 Generate code that uses (does not use) the load multiple word
1 instructions and the store multiple word instructions. These
1 instructions are generated by default on POWER systems, and not
1 generated on PowerPC systems. Do not use '-mmultiple' on
1 little-endian PowerPC systems, since those instructions do not work
1 when the processor is in little-endian mode. The exceptions are
1 PPC740 and PPC750 which permit these instructions in little-endian
1 mode.
1
1 '-mupdate'
1 '-mno-update'
1 Generate code that uses (does not use) the load or store
1 instructions that update the base register to the address of the
1 calculated memory location. These instructions are generated by
1 default. If you use '-mno-update', there is a small window between
1 the time that the stack pointer is updated and the address of the
1 previous frame is stored, which means code that walks the stack
1 frame across interrupts or signals may get corrupted data.
1
1 '-mavoid-indexed-addresses'
1 '-mno-avoid-indexed-addresses'
1 Generate code that tries to avoid (not avoid) the use of indexed
1 load or store instructions. These instructions can incur a
1 performance penalty on Power6 processors in certain situations,
1 such as when stepping through large arrays that cross a 16M
1 boundary. This option is enabled by default when targeting Power6
1 and disabled otherwise.
1
1 '-mfused-madd'
1 '-mno-fused-madd'
1 Generate code that uses (does not use) the floating-point multiply
1 and accumulate instructions. These instructions are generated by
1 default if hardware floating point is used. The machine-dependent
1 '-mfused-madd' option is now mapped to the machine-independent
1 '-ffp-contract=fast' option, and '-mno-fused-madd' is mapped to
1 '-ffp-contract=off'.
1
1 '-mmulhw'
1 '-mno-mulhw'
1 Generate code that uses (does not use) the half-word multiply and
1 multiply-accumulate instructions on the IBM 405, 440, 464 and 476
1 processors. These instructions are generated by default when
1 targeting those processors.
1
1 '-mdlmzb'
1 '-mno-dlmzb'
1 Generate code that uses (does not use) the string-search 'dlmzb'
1 instruction on the IBM 405, 440, 464 and 476 processors. This
1 instruction is generated by default when targeting those
1 processors.
1
1 '-mno-bit-align'
1 '-mbit-align'
1 On System V.4 and embedded PowerPC systems do not (do) force
1 structures and unions that contain bit-fields to be aligned to the
1 base type of the bit-field.
1
1 For example, by default a structure containing nothing but 8
1 'unsigned' bit-fields of length 1 is aligned to a 4-byte boundary
1 and has a size of 4 bytes. By using '-mno-bit-align', the
1 structure is aligned to a 1-byte boundary and is 1 byte in size.
1
1 '-mno-strict-align'
1 '-mstrict-align'
1 On System V.4 and embedded PowerPC systems do not (do) assume that
1 unaligned memory references are handled by the system.
1
1 '-mrelocatable'
1 '-mno-relocatable'
1 Generate code that allows (does not allow) a static executable to
1 be relocated to a different address at run time. A simple embedded
1 PowerPC system loader should relocate the entire contents of
1 '.got2' and 4-byte locations listed in the '.fixup' section, a
1 table of 32-bit addresses generated by this option. For this to
1 work, all objects linked together must be compiled with
1 '-mrelocatable' or '-mrelocatable-lib'. '-mrelocatable' code
1 aligns the stack to an 8-byte boundary.
1
1 '-mrelocatable-lib'
1 '-mno-relocatable-lib'
1 Like '-mrelocatable', '-mrelocatable-lib' generates a '.fixup'
1 section to allow static executables to be relocated at run time,
1 but '-mrelocatable-lib' does not use the smaller stack alignment of
1 '-mrelocatable'. Objects compiled with '-mrelocatable-lib' may be
1 linked with objects compiled with any combination of the
1 '-mrelocatable' options.
1
1 '-mno-toc'
1 '-mtoc'
1 On System V.4 and embedded PowerPC systems do not (do) assume that
1 register 2 contains a pointer to a global area pointing to the
1 addresses used in the program.
1
1 '-mlittle'
1 '-mlittle-endian'
1 On System V.4 and embedded PowerPC systems compile code for the
1 processor in little-endian mode. The '-mlittle-endian' option is
1 the same as '-mlittle'.
1
1 '-mbig'
1 '-mbig-endian'
1 On System V.4 and embedded PowerPC systems compile code for the
1 processor in big-endian mode. The '-mbig-endian' option is the
1 same as '-mbig'.
1
1 '-mdynamic-no-pic'
1 On Darwin and Mac OS X systems, compile code so that it is not
1 relocatable, but that its external references are relocatable. The
1 resulting code is suitable for applications, but not shared
1 libraries.
1
1 '-msingle-pic-base'
1 Treat the register used for PIC addressing as read-only, rather
1 than loading it in the prologue for each function. The runtime
1 system is responsible for initializing this register with an
1 appropriate value before execution begins.
1
1 '-mprioritize-restricted-insns=PRIORITY'
1 This option controls the priority that is assigned to dispatch-slot
1 restricted instructions during the second scheduling pass. The
1 argument PRIORITY takes the value '0', '1', or '2' to assign no,
1 highest, or second-highest (respectively) priority to dispatch-slot
1 restricted instructions.
1
1 '-msched-costly-dep=DEPENDENCE_TYPE'
1 This option controls which dependences are considered costly by the
1 target during instruction scheduling. The argument DEPENDENCE_TYPE
1 takes one of the following values:
1
1 'no'
1 No dependence is costly.
1
1 'all'
1 All dependences are costly.
1
1 'true_store_to_load'
1 A true dependence from store to load is costly.
1
1 'store_to_load'
1 Any dependence from store to load is costly.
1
1 NUMBER
1 Any dependence for which the latency is greater than or equal
1 to NUMBER is costly.
1
1 '-minsert-sched-nops=SCHEME'
1 This option controls which NOP insertion scheme is used during the
1 second scheduling pass. The argument SCHEME takes one of the
1 following values:
1
1 'no'
1 Don't insert NOPs.
1
1 'pad'
1 Pad with NOPs any dispatch group that has vacant issue slots,
1 according to the scheduler's grouping.
1
1 'regroup_exact'
1 Insert NOPs to force costly dependent insns into separate
1 groups. Insert exactly as many NOPs as needed to force an
1 insn to a new group, according to the estimated processor
1 grouping.
1
1 NUMBER
1 Insert NOPs to force costly dependent insns into separate
1 groups. Insert NUMBER NOPs to force an insn to a new group.
1
1 '-mcall-sysv'
1 On System V.4 and embedded PowerPC systems compile code using
1 calling conventions that adhere to the March 1995 draft of the
1 System V Application Binary Interface, PowerPC processor
1 supplement. This is the default unless you configured GCC using
1 'powerpc-*-eabiaix'.
1
1 '-mcall-sysv-eabi'
1 '-mcall-eabi'
1 Specify both '-mcall-sysv' and '-meabi' options.
1
1 '-mcall-sysv-noeabi'
1 Specify both '-mcall-sysv' and '-mno-eabi' options.
1
1 '-mcall-aixdesc'
1 On System V.4 and embedded PowerPC systems compile code for the AIX
1 operating system.
1
1 '-mcall-linux'
1 On System V.4 and embedded PowerPC systems compile code for the
1 Linux-based GNU system.
1
1 '-mcall-freebsd'
1 On System V.4 and embedded PowerPC systems compile code for the
1 FreeBSD operating system.
1
1 '-mcall-netbsd'
1 On System V.4 and embedded PowerPC systems compile code for the
1 NetBSD operating system.
1
1 '-mcall-openbsd'
1 On System V.4 and embedded PowerPC systems compile code for the
1 OpenBSD operating system.
1
1 '-mtraceback=TRACEBACK_TYPE'
1 Select the type of traceback table. Valid values for
1 TRACEBACK_TYPE are 'full', 'part', and 'no'.
1
1 '-maix-struct-return'
1 Return all structures in memory (as specified by the AIX ABI).
1
1 '-msvr4-struct-return'
1 Return structures smaller than 8 bytes in registers (as specified
1 by the SVR4 ABI).
1
1 '-mabi=ABI-TYPE'
1 Extend the current ABI with a particular extension, or remove such
1 extension. Valid values are 'altivec', 'no-altivec', 'spe',
1 'no-spe', 'ibmlongdouble', 'ieeelongdouble', 'elfv1', 'elfv2'.
1
1 '-mabi=ibmlongdouble'
1 Change the current ABI to use IBM extended-precision long double.
1 This is not likely to work if your system defaults to using IEEE
1 extended-precision long double. If you change the long double type
1 from IEEE extended-precision, the compiler will issue a warning
1 unless you use the '-Wno-psabi' option. Requires
1 '-mlong-double-128' to be enabled.
1
1 '-mabi=ieeelongdouble'
1 Change the current ABI to use IEEE extended-precision long double.
1 This is not likely to work if your system defaults to using IBM
1 extended-precision long double. If you change the long double type
1 from IBM extended-precision, the compiler will issue a warning
1 unless you use the '-Wno-psabi' option. Requires
1 '-mlong-double-128' to be enabled.
1
1 '-mabi=elfv1'
1 Change the current ABI to use the ELFv1 ABI. This is the default
1 ABI for big-endian PowerPC 64-bit Linux. Overriding the default
1 ABI requires special system support and is likely to fail in
1 spectacular ways.
1
1 '-mabi=elfv2'
1 Change the current ABI to use the ELFv2 ABI. This is the default
1 ABI for little-endian PowerPC 64-bit Linux. Overriding the default
1 ABI requires special system support and is likely to fail in
1 spectacular ways.
1
1 '-mgnu-attribute'
1 '-mno-gnu-attribute'
1 Emit .gnu_attribute assembly directives to set tag/value pairs in a
1 .gnu.attributes section that specify ABI variations in function
1 parameters or return values.
1
1 '-mprototype'
1 '-mno-prototype'
1 On System V.4 and embedded PowerPC systems assume that all calls to
1 variable argument functions are properly prototyped. Otherwise,
1 the compiler must insert an instruction before every non-prototyped
1 call to set or clear bit 6 of the condition code register ('CR') to
1 indicate whether floating-point values are passed in the
1 floating-point registers in case the function takes variable
1 arguments. With '-mprototype', only calls to prototyped variable
1 argument functions set or clear the bit.
1
1 '-msim'
1 On embedded PowerPC systems, assume that the startup module is
1 called 'sim-crt0.o' and that the standard C libraries are
1 'libsim.a' and 'libc.a'. This is the default for
1 'powerpc-*-eabisim' configurations.
1
1 '-mmvme'
1 On embedded PowerPC systems, assume that the startup module is
1 called 'crt0.o' and the standard C libraries are 'libmvme.a' and
1 'libc.a'.
1
1 '-mads'
1 On embedded PowerPC systems, assume that the startup module is
1 called 'crt0.o' and the standard C libraries are 'libads.a' and
1 'libc.a'.
1
1 '-myellowknife'
1 On embedded PowerPC systems, assume that the startup module is
1 called 'crt0.o' and the standard C libraries are 'libyk.a' and
1 'libc.a'.
1
1 '-mvxworks'
1 On System V.4 and embedded PowerPC systems, specify that you are
1 compiling for a VxWorks system.
1
1 '-memb'
1 On embedded PowerPC systems, set the 'PPC_EMB' bit in the ELF flags
1 header to indicate that 'eabi' extended relocations are used.
1
1 '-meabi'
1 '-mno-eabi'
1 On System V.4 and embedded PowerPC systems do (do not) adhere to
1 the Embedded Applications Binary Interface (EABI), which is a set
1 of modifications to the System V.4 specifications. Selecting
1 '-meabi' means that the stack is aligned to an 8-byte boundary, a
1 function '__eabi' is called from 'main' to set up the EABI
1 environment, and the '-msdata' option can use both 'r2' and 'r13'
1 to point to two separate small data areas. Selecting '-mno-eabi'
1 means that the stack is aligned to a 16-byte boundary, no EABI
1 initialization function is called from 'main', and the '-msdata'
1 option only uses 'r13' to point to a single small data area. The
1 '-meabi' option is on by default if you configured GCC using one of
1 the 'powerpc*-*-eabi*' options.
1
1 '-msdata=eabi'
1 On System V.4 and embedded PowerPC systems, put small initialized
1 'const' global and static data in the '.sdata2' section, which is
1 pointed to by register 'r2'. Put small initialized non-'const'
1 global and static data in the '.sdata' section, which is pointed to
1 by register 'r13'. Put small uninitialized global and static data
1 in the '.sbss' section, which is adjacent to the '.sdata' section.
1 The '-msdata=eabi' option is incompatible with the '-mrelocatable'
1 option. The '-msdata=eabi' option also sets the '-memb' option.
1
1 '-msdata=sysv'
1 On System V.4 and embedded PowerPC systems, put small global and
1 static data in the '.sdata' section, which is pointed to by
1 register 'r13'. Put small uninitialized global and static data in
1 the '.sbss' section, which is adjacent to the '.sdata' section.
1 The '-msdata=sysv' option is incompatible with the '-mrelocatable'
1 option.
1
1 '-msdata=default'
1 '-msdata'
1 On System V.4 and embedded PowerPC systems, if '-meabi' is used,
1 compile code the same as '-msdata=eabi', otherwise compile code the
1 same as '-msdata=sysv'.
1
1 '-msdata=data'
1 On System V.4 and embedded PowerPC systems, put small global data
1 in the '.sdata' section. Put small uninitialized global data in
1 the '.sbss' section. Do not use register 'r13' to address small
1 data however. This is the default behavior unless other '-msdata'
1 options are used.
1
1 '-msdata=none'
1 '-mno-sdata'
1 On embedded PowerPC systems, put all initialized global and static
1 data in the '.data' section, and all uninitialized data in the
1 '.bss' section.
1
1 '-mreadonly-in-sdata'
1 '-mreadonly-in-sdata'
1 Put read-only objects in the '.sdata' section as well. This is the
1 default.
1
1 '-mblock-move-inline-limit=NUM'
1 Inline all block moves (such as calls to 'memcpy' or structure
1 copies) less than or equal to NUM bytes. The minimum value for NUM
1 is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets. The
1 default value is target-specific.
1
1 '-mblock-compare-inline-limit=NUM'
1 Generate non-looping inline code for all block compares (such as
1 calls to 'memcmp' or structure compares) less than or equal to NUM
1 bytes. If NUM is 0, all inline expansion (non-loop and loop) of
1 block compare is disabled. The default value is target-specific.
1
1 '-mblock-compare-inline-loop-limit=NUM'
1 Generate an inline expansion using loop code for all block compares
1 that are less than or equal to NUM bytes, but greater than the
1 limit for non-loop inline block compare expansion. If the block
1 length is not constant, at most NUM bytes will be compared before
1 'memcmp' is called to compare the remainder of the block. The
1 default value is target-specific.
1
1 '-mstring-compare-inline-limit=NUM'
1 Generate at most NUM pairs of load instructions to compare the
1 string inline. If the difference or end of string is not found at
1 the end of the inline compare a call to 'strcmp' or 'strncmp' will
1 take care of the rest of the comparison. The default is 8 pairs of
1 loads, which will compare 64 bytes on a 64-bit target and 32 bytes
1 on a 32-bit target.
1
1 '-G NUM'
1 On embedded PowerPC systems, put global and static items less than
1 or equal to NUM bytes into the small data or BSS sections instead
1 of the normal data or BSS section. By default, NUM is 8. The '-G
1 NUM' switch is also passed to the linker. All modules should be
1 compiled with the same '-G NUM' value.
1
1 '-mregnames'
1 '-mno-regnames'
1 On System V.4 and embedded PowerPC systems do (do not) emit
1 register names in the assembly language output using symbolic
1 forms.
1
1 '-mlongcall'
1 '-mno-longcall'
1 By default assume that all calls are far away so that a longer and
1 more expensive calling sequence is required. This is required for
1 calls farther than 32 megabytes (33,554,432 bytes) from the current
1 location. A short call is generated if the compiler knows the call
1 cannot be that far away. This setting can be overridden by the
1 'shortcall' function attribute, or by '#pragma longcall(0)'.
1
1 Some linkers are capable of detecting out-of-range calls and
1 generating glue code on the fly. On these systems, long calls are
1 unnecessary and generate slower code. As of this writing, the AIX
1 linker can do this, as can the GNU linker for PowerPC/64. It is
1 planned to add this feature to the GNU linker for 32-bit PowerPC
1 systems as well.
1
1 On Darwin/PPC systems, '#pragma longcall' generates 'jbsr callee,
1 L42', plus a "branch island" (glue code). The two target addresses
1 represent the callee and the branch island. The Darwin/PPC linker
1 prefers the first address and generates a 'bl callee' if the PPC
1 'bl' instruction reaches the callee directly; otherwise, the linker
1 generates 'bl L42' to call the branch island. The branch island is
1 appended to the body of the calling function; it computes the full
1 32-bit address of the callee and jumps to it.
1
1 On Mach-O (Darwin) systems, this option directs the compiler emit
1 to the glue for every direct call, and the Darwin linker decides
1 whether to use or discard it.
1
1 In the future, GCC may ignore all longcall specifications when the
1 linker is known to generate glue.
1
1 '-mtls-markers'
1 '-mno-tls-markers'
1 Mark (do not mark) calls to '__tls_get_addr' with a relocation
1 specifying the function argument. The relocation allows the linker
1 to reliably associate function call with argument setup
1 instructions for TLS optimization, which in turn allows GCC to
1 better schedule the sequence.
1
1 '-mrecip'
1 '-mno-recip'
1 This option enables use of the reciprocal estimate and reciprocal
1 square root estimate instructions with additional Newton-Raphson
1 steps to increase precision instead of doing a divide or square
1 root and divide for floating-point arguments. You should use the
1 '-ffast-math' option when using '-mrecip' (or at least
1 '-funsafe-math-optimizations', '-ffinite-math-only',
1 '-freciprocal-math' and '-fno-trapping-math'). Note that while the
1 throughput of the sequence is generally higher than the throughput
1 of the non-reciprocal instruction, the precision of the sequence
1 can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals
1 0.99999994) for reciprocal square roots.
1
1 '-mrecip=OPT'
1 This option controls which reciprocal estimate instructions may be
1 used. OPT is a comma-separated list of options, which may be
1 preceded by a '!' to invert the option:
1
1 'all'
1 Enable all estimate instructions.
1
1 'default'
1 Enable the default instructions, equivalent to '-mrecip'.
1
1 'none'
1 Disable all estimate instructions, equivalent to '-mno-recip'.
1
1 'div'
1 Enable the reciprocal approximation instructions for both
1 single and double precision.
1
1 'divf'
1 Enable the single-precision reciprocal approximation
1 instructions.
1
1 'divd'
1 Enable the double-precision reciprocal approximation
1 instructions.
1
1 'rsqrt'
1 Enable the reciprocal square root approximation instructions
1 for both single and double precision.
1
1 'rsqrtf'
1 Enable the single-precision reciprocal square root
1 approximation instructions.
1
1 'rsqrtd'
1 Enable the double-precision reciprocal square root
1 approximation instructions.
1
1 So, for example, '-mrecip=all,!rsqrtd' enables all of the
1 reciprocal estimate instructions, except for the 'FRSQRTE',
1 'XSRSQRTEDP', and 'XVRSQRTEDP' instructions which handle the
1 double-precision reciprocal square root calculations.
1
1 '-mrecip-precision'
1 '-mno-recip-precision'
1 Assume (do not assume) that the reciprocal estimate instructions
1 provide higher-precision estimates than is mandated by the PowerPC
1 ABI. Selecting '-mcpu=power6', '-mcpu=power7' or '-mcpu=power8'
1 automatically selects '-mrecip-precision'. The double-precision
1 square root estimate instructions are not generated by default on
1 low-precision machines, since they do not provide an estimate that
1 converges after three steps.
1
1 '-mveclibabi=TYPE'
1 Specifies the ABI type to use for vectorizing intrinsics using an
1 external library. The only type supported at present is 'mass',
1 which specifies to use IBM's Mathematical Acceleration Subsystem
1 (MASS) libraries for vectorizing intrinsics using external
1 libraries. GCC currently emits calls to 'acosd2', 'acosf4',
1 'acoshd2', 'acoshf4', 'asind2', 'asinf4', 'asinhd2', 'asinhf4',
1 'atan2d2', 'atan2f4', 'atand2', 'atanf4', 'atanhd2', 'atanhf4',
1 'cbrtd2', 'cbrtf4', 'cosd2', 'cosf4', 'coshd2', 'coshf4', 'erfcd2',
1 'erfcf4', 'erfd2', 'erff4', 'exp2d2', 'exp2f4', 'expd2', 'expf4',
1 'expm1d2', 'expm1f4', 'hypotd2', 'hypotf4', 'lgammad2', 'lgammaf4',
1 'log10d2', 'log10f4', 'log1pd2', 'log1pf4', 'log2d2', 'log2f4',
1 'logd2', 'logf4', 'powd2', 'powf4', 'sind2', 'sinf4', 'sinhd2',
1 'sinhf4', 'sqrtd2', 'sqrtf4', 'tand2', 'tanf4', 'tanhd2', and
1 'tanhf4' when generating code for power7. Both '-ftree-vectorize'
1 and '-funsafe-math-optimizations' must also be enabled. The MASS
1 libraries must be specified at link time.
1
1 '-mfriz'
1 '-mno-friz'
1 Generate (do not generate) the 'friz' instruction when the
1 '-funsafe-math-optimizations' option is used to optimize rounding
1 of floating-point values to 64-bit integer and back to floating
1 point. The 'friz' instruction does not return the same value if
1 the floating-point number is too large to fit in an integer.
1
1 '-mpointers-to-nested-functions'
1 '-mno-pointers-to-nested-functions'
1 Generate (do not generate) code to load up the static chain
1 register ('r11') when calling through a pointer on AIX and 64-bit
1 Linux systems where a function pointer points to a 3-word
1 descriptor giving the function address, TOC value to be loaded in
1 register 'r2', and static chain value to be loaded in register
1 'r11'. The '-mpointers-to-nested-functions' is on by default. You
1 cannot call through pointers to nested functions or pointers to
1 functions compiled in other languages that use the static chain if
1 you use '-mno-pointers-to-nested-functions'.
1
1 '-msave-toc-indirect'
1 '-mno-save-toc-indirect'
1 Generate (do not generate) code to save the TOC value in the
1 reserved stack location in the function prologue if the function
1 calls through a pointer on AIX and 64-bit Linux systems. If the
1 TOC value is not saved in the prologue, it is saved just before the
1 call through the pointer. The '-mno-save-toc-indirect' option is
1 the default.
1
1 '-mcompat-align-parm'
1 '-mno-compat-align-parm'
1 Generate (do not generate) code to pass structure parameters with a
1 maximum alignment of 64 bits, for compatibility with older versions
1 of GCC.
1
1 Older versions of GCC (prior to 4.9.0) incorrectly did not align a
1 structure parameter on a 128-bit boundary when that structure
1 contained a member requiring 128-bit alignment. This is corrected
1 in more recent versions of GCC. This option may be used to generate
1 code that is compatible with functions compiled with older versions
1 of GCC.
1
1 The '-mno-compat-align-parm' option is the default.
1
1 '-mstack-protector-guard=GUARD'
1 '-mstack-protector-guard-reg=REG'
1 '-mstack-protector-guard-offset=OFFSET'
1 '-mstack-protector-guard-symbol=SYMBOL'
1 Generate stack protection code using canary at GUARD. Supported
1 locations are 'global' for global canary or 'tls' for per-thread
1 canary in the TLS block (the default with GNU libc version 2.4 or
1 later).
1
1 With the latter choice the options
1 '-mstack-protector-guard-reg=REG' and
1 '-mstack-protector-guard-offset=OFFSET' furthermore specify which
1 register to use as base register for reading the canary, and from
1 what offset from that base register. The default for those is as
1 specified in the relevant ABI.
1 '-mstack-protector-guard-symbol=SYMBOL' overrides the offset with a
1 symbol reference to a canary in the TLS block.
1