gcc: MIPS Options
1
1 3.18.26 MIPS Options
1 --------------------
1
1 '-EB'
1 Generate big-endian code.
1
1 '-EL'
1 Generate little-endian code. This is the default for 'mips*el-*-*'
1 configurations.
1
1 '-march=ARCH'
1 Generate code that runs on ARCH, which can be the name of a generic
1 MIPS ISA, or the name of a particular processor. The ISA names
1 are: 'mips1', 'mips2', 'mips3', 'mips4', 'mips32', 'mips32r2',
1 'mips32r3', 'mips32r5', 'mips32r6', 'mips64', 'mips64r2',
1 'mips64r3', 'mips64r5' and 'mips64r6'. The processor names are:
1 '4kc', '4km', '4kp', '4ksc', '4kec', '4kem', '4kep', '4ksd', '5kc',
1 '5kf', '20kc', '24kc', '24kf2_1', '24kf1_1', '24kec', '24kef2_1',
1 '24kef1_1', '34kc', '34kf2_1', '34kf1_1', '34kn', '74kc',
1 '74kf2_1', '74kf1_1', '74kf3_2', '1004kc', '1004kf2_1',
1 '1004kf1_1', 'i6400', 'interaptiv', 'loongson2e', 'loongson2f',
1 'loongson3a', 'm4k', 'm14k', 'm14kc', 'm14ke', 'm14kec', 'm5100',
1 'm5101', 'octeon', 'octeon+', 'octeon2', 'octeon3', 'orion',
1 'p5600', 'r2000', 'r3000', 'r3900', 'r4000', 'r4400', 'r4600',
1 'r4650', 'r4700', 'r6000', 'r8000', 'rm7000', 'rm9000', 'r10000',
1 'r12000', 'r14000', 'r16000', 'sb1', 'sr71000', 'vr4100', 'vr4111',
1 'vr4120', 'vr4130', 'vr4300', 'vr5000', 'vr5400', 'vr5500', 'xlr'
1 and 'xlp'. The special value 'from-abi' selects the most
1 compatible architecture for the selected ABI (that is, 'mips1' for
1 32-bit ABIs and 'mips3' for 64-bit ABIs).
1
1 The native Linux/GNU toolchain also supports the value 'native',
1 which selects the best architecture option for the host processor.
1 '-march=native' has no effect if GCC does not recognize the
1 processor.
1
1 In processor names, a final '000' can be abbreviated as 'k' (for
1 example, '-march=r2k'). Prefixes are optional, and 'vr' may be
1 written 'r'.
1
1 Names of the form 'Nf2_1' refer to processors with FPUs clocked at
1 half the rate of the core, names of the form 'Nf1_1' refer to
1 processors with FPUs clocked at the same rate as the core, and
1 names of the form 'Nf3_2' refer to processors with FPUs clocked a
1 ratio of 3:2 with respect to the core. For compatibility reasons,
1 'Nf' is accepted as a synonym for 'Nf2_1' while 'Nx' and 'Bfx' are
1 accepted as synonyms for 'Nf1_1'.
1
1 GCC defines two macros based on the value of this option. The
1 first is '_MIPS_ARCH', which gives the name of target architecture,
1 as a string. The second has the form '_MIPS_ARCH_FOO', where FOO
1 is the capitalized value of '_MIPS_ARCH'. For example,
1 '-march=r2000' sets '_MIPS_ARCH' to '"r2000"' and defines the macro
1 '_MIPS_ARCH_R2000'.
1
1 Note that the '_MIPS_ARCH' macro uses the processor names given
1 above. In other words, it has the full prefix and does not
1 abbreviate '000' as 'k'. In the case of 'from-abi', the macro
1 names the resolved architecture (either '"mips1"' or '"mips3"').
1 It names the default architecture when no '-march' option is given.
1
1 '-mtune=ARCH'
1 Optimize for ARCH. Among other things, this option controls the
1 way instructions are scheduled, and the perceived cost of
1 arithmetic operations. The list of ARCH values is the same as for
1 '-march'.
1
1 When this option is not used, GCC optimizes for the processor
1 specified by '-march'. By using '-march' and '-mtune' together, it
1 is possible to generate code that runs on a family of processors,
1 but optimize the code for one particular member of that family.
1
1 '-mtune' defines the macros '_MIPS_TUNE' and '_MIPS_TUNE_FOO',
1 which work in the same way as the '-march' ones described above.
1
1 '-mips1'
1 Equivalent to '-march=mips1'.
1
1 '-mips2'
1 Equivalent to '-march=mips2'.
1
1 '-mips3'
1 Equivalent to '-march=mips3'.
1
1 '-mips4'
1 Equivalent to '-march=mips4'.
1
1 '-mips32'
1 Equivalent to '-march=mips32'.
1
1 '-mips32r3'
1 Equivalent to '-march=mips32r3'.
1
1 '-mips32r5'
1 Equivalent to '-march=mips32r5'.
1
1 '-mips32r6'
1 Equivalent to '-march=mips32r6'.
1
1 '-mips64'
1 Equivalent to '-march=mips64'.
1
1 '-mips64r2'
1 Equivalent to '-march=mips64r2'.
1
1 '-mips64r3'
1 Equivalent to '-march=mips64r3'.
1
1 '-mips64r5'
1 Equivalent to '-march=mips64r5'.
1
1 '-mips64r6'
1 Equivalent to '-march=mips64r6'.
1
1 '-mips16'
1 '-mno-mips16'
1 Generate (do not generate) MIPS16 code. If GCC is targeting a
1 MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
1
1 MIPS16 code generation can also be controlled on a per-function
11 basis by means of 'mips16' and 'nomips16' attributes. ⇒
Function Attributes, for more information.
1
1 '-mflip-mips16'
1 Generate MIPS16 code on alternating functions. This option is
1 provided for regression testing of mixed MIPS16/non-MIPS16 code
1 generation, and is not intended for ordinary use in compiling user
1 code.
1
1 '-minterlink-compressed'
1 '-mno-interlink-compressed'
1 Require (do not require) that code using the standard
1 (uncompressed) MIPS ISA be link-compatible with MIPS16 and
1 microMIPS code, and vice versa.
1
1 For example, code using the standard ISA encoding cannot jump
1 directly to MIPS16 or microMIPS code; it must either use a call or
1 an indirect jump. '-minterlink-compressed' therefore disables
1 direct jumps unless GCC knows that the target of the jump is not
1 compressed.
1
1 '-minterlink-mips16'
1 '-mno-interlink-mips16'
1 Aliases of '-minterlink-compressed' and
1 '-mno-interlink-compressed'. These options predate the microMIPS
1 ASE and are retained for backwards compatibility.
1
1 '-mabi=32'
1 '-mabi=o64'
1 '-mabi=n32'
1 '-mabi=64'
1 '-mabi=eabi'
1 Generate code for the given ABI.
1
1 Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
1 generates 64-bit code when you select a 64-bit architecture, but
1 you can use '-mgp32' to get 32-bit code instead.
1
1 For information about the O64 ABI, see
1 <http://gcc.gnu.org/projects/mipso64-abi.html>.
1
1 GCC supports a variant of the o32 ABI in which floating-point
1 registers are 64 rather than 32 bits wide. You can select this
1 combination with '-mabi=32' '-mfp64'. This ABI relies on the
1 'mthc1' and 'mfhc1' instructions and is therefore only supported
1 for MIPS32R2, MIPS32R3 and MIPS32R5 processors.
1
1 The register assignments for arguments and return values remain the
1 same, but each scalar value is passed in a single 64-bit register
1 rather than a pair of 32-bit registers. For example, scalar
1 floating-point values are returned in '$f0' only, not a '$f0'/'$f1'
1 pair. The set of call-saved registers also remains the same in
1 that the even-numbered double-precision registers are saved.
1
1 Two additional variants of the o32 ABI are supported to enable a
1 transition from 32-bit to 64-bit registers. These are FPXX
1 ('-mfpxx') and FP64A ('-mfp64' '-mno-odd-spreg'). The FPXX
1 extension mandates that all code must execute correctly when run
1 using 32-bit or 64-bit registers. The code can be interlinked with
1 either FP32 or FP64, but not both. The FP64A extension is similar
1 to the FP64 extension but forbids the use of odd-numbered
1 single-precision registers. This can be used in conjunction with
1 the 'FRE' mode of FPUs in MIPS32R5 processors and allows both FP32
1 and FP64A code to interlink and run in the same process without
1 changing FPU modes.
1
1 '-mabicalls'
1 '-mno-abicalls'
1 Generate (do not generate) code that is suitable for SVR4-style
1 dynamic objects. '-mabicalls' is the default for SVR4-based
1 systems.
1
1 '-mshared'
1 '-mno-shared'
1 Generate (do not generate) code that is fully position-independent,
1 and that can therefore be linked into shared libraries. This
1 option only affects '-mabicalls'.
1
1 All '-mabicalls' code has traditionally been position-independent,
1 regardless of options like '-fPIC' and '-fpic'. However, as an
1 extension, the GNU toolchain allows executables to use absolute
1 accesses for locally-binding symbols. It can also use shorter GP
1 initialization sequences and generate direct calls to
1 locally-defined functions. This mode is selected by '-mno-shared'.
1
1 '-mno-shared' depends on binutils 2.16 or higher and generates
1 objects that can only be linked by the GNU linker. However, the
1 option does not affect the ABI of the final executable; it only
1 affects the ABI of relocatable objects. Using '-mno-shared'
1 generally makes executables both smaller and quicker.
1
1 '-mshared' is the default.
1
1 '-mplt'
1 '-mno-plt'
1 Assume (do not assume) that the static and dynamic linkers support
1 PLTs and copy relocations. This option only affects '-mno-shared
1 -mabicalls'. For the n64 ABI, this option has no effect without
1 '-msym32'.
1
1 You can make '-mplt' the default by configuring GCC with
1 '--with-mips-plt'. The default is '-mno-plt' otherwise.
1
1 '-mxgot'
1 '-mno-xgot'
1 Lift (do not lift) the usual restrictions on the size of the global
1 offset table.
1
1 GCC normally uses a single instruction to load values from the GOT.
1 While this is relatively efficient, it only works if the GOT is
1 smaller than about 64k. Anything larger causes the linker to
1 report an error such as:
1
1 relocation truncated to fit: R_MIPS_GOT16 foobar
1
1 If this happens, you should recompile your code with '-mxgot'.
1 This works with very large GOTs, although the code is also less
1 efficient, since it takes three instructions to fetch the value of
1 a global symbol.
1
1 Note that some linkers can create multiple GOTs. If you have such
1 a linker, you should only need to use '-mxgot' when a single object
1 file accesses more than 64k's worth of GOT entries. Very few do.
1
1 These options have no effect unless GCC is generating position
1 independent code.
1
1 '-mgp32'
1 Assume that general-purpose registers are 32 bits wide.
1
1 '-mgp64'
1 Assume that general-purpose registers are 64 bits wide.
1
1 '-mfp32'
1 Assume that floating-point registers are 32 bits wide.
1
1 '-mfp64'
1 Assume that floating-point registers are 64 bits wide.
1
1 '-mfpxx'
1 Do not assume the width of floating-point registers.
1
1 '-mhard-float'
1 Use floating-point coprocessor instructions.
1
1 '-msoft-float'
1 Do not use floating-point coprocessor instructions. Implement
1 floating-point calculations using library calls instead.
1
1 '-mno-float'
1 Equivalent to '-msoft-float', but additionally asserts that the
1 program being compiled does not perform any floating-point
1 operations. This option is presently supported only by some
1 bare-metal MIPS configurations, where it may select a special set
1 of libraries that lack all floating-point support (including, for
1 example, the floating-point 'printf' formats). If code compiled
1 with '-mno-float' accidentally contains floating-point operations,
1 it is likely to suffer a link-time or run-time failure.
1
1 '-msingle-float'
1 Assume that the floating-point coprocessor only supports
1 single-precision operations.
1
1 '-mdouble-float'
1 Assume that the floating-point coprocessor supports
1 double-precision operations. This is the default.
1
1 '-modd-spreg'
1 '-mno-odd-spreg'
1 Enable the use of odd-numbered single-precision floating-point
1 registers for the o32 ABI. This is the default for processors that
1 are known to support these registers. When using the o32 FPXX ABI,
1 '-mno-odd-spreg' is set by default.
1
1 '-mabs=2008'
1 '-mabs=legacy'
1 These options control the treatment of the special not-a-number
1 (NaN) IEEE 754 floating-point data with the 'abs.fmt' and 'neg.fmt'
1 machine instructions.
1
1 By default or when '-mabs=legacy' is used the legacy treatment is
1 selected. In this case these instructions are considered
1 arithmetic and avoided where correct operation is required and the
1 input operand might be a NaN. A longer sequence of instructions
1 that manipulate the sign bit of floating-point datum manually is
1 used instead unless the '-ffinite-math-only' option has also been
1 specified.
1
1 The '-mabs=2008' option selects the IEEE 754-2008 treatment. In
1 this case these instructions are considered non-arithmetic and
1 therefore operating correctly in all cases, including in particular
1 where the input operand is a NaN. These instructions are therefore
1 always used for the respective operations.
1
1 '-mnan=2008'
1 '-mnan=legacy'
1 These options control the encoding of the special not-a-number
1 (NaN) IEEE 754 floating-point data.
1
1 The '-mnan=legacy' option selects the legacy encoding. In this
1 case quiet NaNs (qNaNs) are denoted by the first bit of their
1 trailing significand field being 0, whereas signaling NaNs (sNaNs)
1 are denoted by the first bit of their trailing significand field
1 being 1.
1
1 The '-mnan=2008' option selects the IEEE 754-2008 encoding. In
1 this case qNaNs are denoted by the first bit of their trailing
1 significand field being 1, whereas sNaNs are denoted by the first
1 bit of their trailing significand field being 0.
1
1 The default is '-mnan=legacy' unless GCC has been configured with
1 '--with-nan=2008'.
1
1 '-mllsc'
1 '-mno-llsc'
1 Use (do not use) 'll', 'sc', and 'sync' instructions to implement
1 atomic memory built-in functions. When neither option is
1 specified, GCC uses the instructions if the target architecture
1 supports them.
1
1 '-mllsc' is useful if the runtime environment can emulate the
1 instructions and '-mno-llsc' can be useful when compiling for
1 nonstandard ISAs. You can make either option the default by
1 configuring GCC with '--with-llsc' and '--without-llsc'
1 respectively. '--with-llsc' is the default for some
1 configurations; see the installation documentation for details.
1
1 '-mdsp'
1 '-mno-dsp'
11 Use (do not use) revision 1 of the MIPS DSP ASE. ⇒MIPS DSP
Built-in Functions. This option defines the preprocessor macro
1 '__mips_dsp'. It also defines '__mips_dsp_rev' to 1.
1
1 '-mdspr2'
1 '-mno-dspr2'
11 Use (do not use) revision 2 of the MIPS DSP ASE. ⇒MIPS DSP
Built-in Functions. This option defines the preprocessor macros
1 '__mips_dsp' and '__mips_dspr2'. It also defines '__mips_dsp_rev'
1 to 2.
1
1 '-msmartmips'
1 '-mno-smartmips'
1 Use (do not use) the MIPS SmartMIPS ASE.
1
1 '-mpaired-single'
1 '-mno-paired-single'
11 Use (do not use) paired-single floating-point instructions. ⇒
MIPS Paired-Single Support. This option requires hardware
1 floating-point support to be enabled.
1
1 '-mdmx'
1 '-mno-mdmx'
1 Use (do not use) MIPS Digital Media Extension instructions. This
1 option can only be used when generating 64-bit code and requires
1 hardware floating-point support to be enabled.
1
1 '-mips3d'
1 '-mno-mips3d'
11 Use (do not use) the MIPS-3D ASE. ⇒MIPS-3D Built-in
Functions. The option '-mips3d' implies '-mpaired-single'.
1
1 '-mmicromips'
1 '-mno-micromips'
1 Generate (do not generate) microMIPS code.
1
1 MicroMIPS code generation can also be controlled on a per-function
11 basis by means of 'micromips' and 'nomicromips' attributes. ⇒
Function Attributes, for more information.
1
1 '-mmt'
1 '-mno-mt'
1 Use (do not use) MT Multithreading instructions.
1
1 '-mmcu'
1 '-mno-mcu'
1 Use (do not use) the MIPS MCU ASE instructions.
1
1 '-meva'
1 '-mno-eva'
1 Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
1
1 '-mvirt'
1 '-mno-virt'
1 Use (do not use) the MIPS Virtualization (VZ) instructions.
1
1 '-mxpa'
1 '-mno-xpa'
1 Use (do not use) the MIPS eXtended Physical Address (XPA)
1 instructions.
1
1 '-mlong64'
1 Force 'long' types to be 64 bits wide. See '-mlong32' for an
1 explanation of the default and the way that the pointer size is
1 determined.
1
1 '-mlong32'
1 Force 'long', 'int', and pointer types to be 32 bits wide.
1
1 The default size of 'int's, 'long's and pointers depends on the
1 ABI. All the supported ABIs use 32-bit 'int's. The n64 ABI uses
1 64-bit 'long's, as does the 64-bit EABI; the others use 32-bit
1 'long's. Pointers are the same size as 'long's, or the same size
1 as integer registers, whichever is smaller.
1
1 '-msym32'
1 '-mno-sym32'
1 Assume (do not assume) that all symbols have 32-bit values,
1 regardless of the selected ABI. This option is useful in
1 combination with '-mabi=64' and '-mno-abicalls' because it allows
1 GCC to generate shorter and faster references to symbolic
1 addresses.
1
1 '-G NUM'
1 Put definitions of externally-visible data in a small data section
1 if that data is no bigger than NUM bytes. GCC can then generate
1 more efficient accesses to the data; see '-mgpopt' for details.
1
1 The default '-G' option depends on the configuration.
1
1 '-mlocal-sdata'
1 '-mno-local-sdata'
1 Extend (do not extend) the '-G' behavior to local data too, such as
1 to static variables in C. '-mlocal-sdata' is the default for all
1 configurations.
1
1 If the linker complains that an application is using too much small
1 data, you might want to try rebuilding the less
1 performance-critical parts with '-mno-local-sdata'. You might also
1 want to build large libraries with '-mno-local-sdata', so that the
1 libraries leave more room for the main program.
1
1 '-mextern-sdata'
1 '-mno-extern-sdata'
1 Assume (do not assume) that externally-defined data is in a small
1 data section if the size of that data is within the '-G' limit.
1 '-mextern-sdata' is the default for all configurations.
1
1 If you compile a module MOD with '-mextern-sdata' '-G NUM'
1 '-mgpopt', and MOD references a variable VAR that is no bigger than
1 NUM bytes, you must make sure that VAR is placed in a small data
1 section. If VAR is defined by another module, you must either
1 compile that module with a high-enough '-G' setting or attach a
1 'section' attribute to VAR's definition. If VAR is common, you
1 must link the application with a high-enough '-G' setting.
1
1 The easiest way of satisfying these restrictions is to compile and
1 link every module with the same '-G' option. However, you may wish
1 to build a library that supports several different small data
1 limits. You can do this by compiling the library with the highest
1 supported '-G' setting and additionally using '-mno-extern-sdata'
1 to stop the library from making assumptions about
1 externally-defined data.
1
1 '-mgpopt'
1 '-mno-gpopt'
1 Use (do not use) GP-relative accesses for symbols that are known to
1 be in a small data section; see '-G', '-mlocal-sdata' and
1 '-mextern-sdata'. '-mgpopt' is the default for all configurations.
1
1 '-mno-gpopt' is useful for cases where the '$gp' register might not
1 hold the value of '_gp'. For example, if the code is part of a
1 library that might be used in a boot monitor, programs that call
1 boot monitor routines pass an unknown value in '$gp'. (In such
1 situations, the boot monitor itself is usually compiled with
1 '-G0'.)
1
1 '-mno-gpopt' implies '-mno-local-sdata' and '-mno-extern-sdata'.
1
1 '-membedded-data'
1 '-mno-embedded-data'
1 Allocate variables to the read-only data section first if possible,
1 then next in the small data section if possible, otherwise in data.
1 This gives slightly slower code than the default, but reduces the
1 amount of RAM required when executing, and thus may be preferred
1 for some embedded systems.
1
1 '-muninit-const-in-rodata'
1 '-mno-uninit-const-in-rodata'
1 Put uninitialized 'const' variables in the read-only data section.
1 This option is only meaningful in conjunction with
1 '-membedded-data'.
1
1 '-mcode-readable=SETTING'
1 Specify whether GCC may generate code that reads from executable
1 sections. There are three possible settings:
1
1 '-mcode-readable=yes'
1 Instructions may freely access executable sections. This is
1 the default setting.
1
1 '-mcode-readable=pcrel'
1 MIPS16 PC-relative load instructions can access executable
1 sections, but other instructions must not do so. This option
1 is useful on 4KSc and 4KSd processors when the code TLBs have
1 the Read Inhibit bit set. It is also useful on processors
1 that can be configured to have a dual instruction/data SRAM
1 interface and that, like the M4K, automatically redirect
1 PC-relative loads to the instruction RAM.
1
1 '-mcode-readable=no'
1 Instructions must not access executable sections. This option
1 can be useful on targets that are configured to have a dual
1 instruction/data SRAM interface but that (unlike the M4K) do
1 not automatically redirect PC-relative loads to the
1 instruction RAM.
1
1 '-msplit-addresses'
1 '-mno-split-addresses'
1 Enable (disable) use of the '%hi()' and '%lo()' assembler
1 relocation operators. This option has been superseded by
1 '-mexplicit-relocs' but is retained for backwards compatibility.
1
1 '-mexplicit-relocs'
1 '-mno-explicit-relocs'
1 Use (do not use) assembler relocation operators when dealing with
1 symbolic addresses. The alternative, selected by
1 '-mno-explicit-relocs', is to use assembler macros instead.
1
1 '-mexplicit-relocs' is the default if GCC was configured to use an
1 assembler that supports relocation operators.
1
1 '-mcheck-zero-division'
1 '-mno-check-zero-division'
1 Trap (do not trap) on integer division by zero.
1
1 The default is '-mcheck-zero-division'.
1
1 '-mdivide-traps'
1 '-mdivide-breaks'
1 MIPS systems check for division by zero by generating either a
1 conditional trap or a break instruction. Using traps results in
1 smaller code, but is only supported on MIPS II and later. Also,
1 some versions of the Linux kernel have a bug that prevents trap
1 from generating the proper signal ('SIGFPE'). Use '-mdivide-traps'
1 to allow conditional traps on architectures that support them and
1 '-mdivide-breaks' to force the use of breaks.
1
1 The default is usually '-mdivide-traps', but this can be overridden
1 at configure time using '--with-divide=breaks'. Divide-by-zero
1 checks can be completely disabled using '-mno-check-zero-division'.
1
1 '-mload-store-pairs'
1 '-mno-load-store-pairs'
1 Enable (disable) an optimization that pairs consecutive load or
1 store instructions to enable load/store bonding. This option is
1 enabled by default but only takes effect when the selected
1 architecture is known to support bonding.
1
1 '-mmemcpy'
1 '-mno-memcpy'
1 Force (do not force) the use of 'memcpy' for non-trivial block
1 moves. The default is '-mno-memcpy', which allows GCC to inline
1 most constant-sized copies.
1
1 '-mlong-calls'
1 '-mno-long-calls'
1 Disable (do not disable) use of the 'jal' instruction. Calling
1 functions using 'jal' is more efficient but requires the caller and
1 callee to be in the same 256 megabyte segment.
1
1 This option has no effect on abicalls code. The default is
1 '-mno-long-calls'.
1
1 '-mmad'
1 '-mno-mad'
1 Enable (disable) use of the 'mad', 'madu' and 'mul' instructions,
1 as provided by the R4650 ISA.
1
1 '-mimadd'
1 '-mno-imadd'
1 Enable (disable) use of the 'madd' and 'msub' integer instructions.
1 The default is '-mimadd' on architectures that support 'madd' and
1 'msub' except for the 74k architecture where it was found to
1 generate slower code.
1
1 '-mfused-madd'
1 '-mno-fused-madd'
1 Enable (disable) use of the floating-point multiply-accumulate
1 instructions, when they are available. The default is
1 '-mfused-madd'.
1
1 On the R8000 CPU when multiply-accumulate instructions are used,
1 the intermediate product is calculated to infinite precision and is
1 not subject to the FCSR Flush to Zero bit. This may be undesirable
1 in some circumstances. On other processors the result is
1 numerically identical to the equivalent computation using separate
1 multiply, add, subtract and negate instructions.
1
1 '-nocpp'
1 Tell the MIPS assembler to not run its preprocessor over user
1 assembler files (with a '.s' suffix) when assembling them.
1
1 '-mfix-24k'
1 '-mno-fix-24k'
1 Work around the 24K E48 (lost data on stores during refill) errata.
1 The workarounds are implemented by the assembler rather than by
1 GCC.
1
1 '-mfix-r4000'
1 '-mno-fix-r4000'
1 Work around certain R4000 CPU errata:
1 - A double-word or a variable shift may give an incorrect result
1 if executed immediately after starting an integer division.
1 - A double-word or a variable shift may give an incorrect result
1 if executed while an integer multiplication is in progress.
1 - An integer division may give an incorrect result if started in
1 a delay slot of a taken branch or a jump.
1
1 '-mfix-r4400'
1 '-mno-fix-r4400'
1 Work around certain R4400 CPU errata:
1 - A double-word or a variable shift may give an incorrect result
1 if executed immediately after starting an integer division.
1
1 '-mfix-r10000'
1 '-mno-fix-r10000'
1 Work around certain R10000 errata:
1 - 'll'/'sc' sequences may not behave atomically on revisions
1 prior to 3.0. They may deadlock on revisions 2.6 and earlier.
1
1 This option can only be used if the target architecture supports
1 branch-likely instructions. '-mfix-r10000' is the default when
1 '-march=r10000' is used; '-mno-fix-r10000' is the default
1 otherwise.
1
1 '-mfix-rm7000'
1 '-mno-fix-rm7000'
1 Work around the RM7000 'dmult'/'dmultu' errata. The workarounds
1 are implemented by the assembler rather than by GCC.
1
1 '-mfix-vr4120'
1 '-mno-fix-vr4120'
1 Work around certain VR4120 errata:
1 - 'dmultu' does not always produce the correct result.
1 - 'div' and 'ddiv' do not always produce the correct result if
1 one of the operands is negative.
1 The workarounds for the division errata rely on special functions
1 in 'libgcc.a'. At present, these functions are only provided by
1 the 'mips64vr*-elf' configurations.
1
1 Other VR4120 errata require a NOP to be inserted between certain
1 pairs of instructions. These errata are handled by the assembler,
1 not by GCC itself.
1
1 '-mfix-vr4130'
1 Work around the VR4130 'mflo'/'mfhi' errata. The workarounds are
1 implemented by the assembler rather than by GCC, although GCC
1 avoids using 'mflo' and 'mfhi' if the VR4130 'macc', 'macchi',
1 'dmacc' and 'dmacchi' instructions are available instead.
1
1 '-mfix-sb1'
1 '-mno-fix-sb1'
1 Work around certain SB-1 CPU core errata. (This flag currently
1 works around the SB-1 revision 2 "F1" and "F2" floating-point
1 errata.)
1
1 '-mr10k-cache-barrier=SETTING'
1 Specify whether GCC should insert cache barriers to avoid the side
1 effects of speculation on R10K processors.
1
1 In common with many processors, the R10K tries to predict the
1 outcome of a conditional branch and speculatively executes
1 instructions from the "taken" branch. It later aborts these
1 instructions if the predicted outcome is wrong. However, on the
1 R10K, even aborted instructions can have side effects.
1
1 This problem only affects kernel stores and, depending on the
1 system, kernel loads. As an example, a speculatively-executed
1 store may load the target memory into cache and mark the cache line
1 as dirty, even if the store itself is later aborted. If a DMA
1 operation writes to the same area of memory before the "dirty" line
1 is flushed, the cached data overwrites the DMA-ed data. See the
1 R10K processor manual for a full description, including other
1 potential problems.
1
1 One workaround is to insert cache barrier instructions before every
1 memory access that might be speculatively executed and that might
1 have side effects even if aborted. '-mr10k-cache-barrier=SETTING'
1 controls GCC's implementation of this workaround. It assumes that
1 aborted accesses to any byte in the following regions does not have
1 side effects:
1
1 1. the memory occupied by the current function's stack frame;
1
1 2. the memory occupied by an incoming stack argument;
1
1 3. the memory occupied by an object with a link-time-constant
1 address.
1
1 It is the kernel's responsibility to ensure that speculative
1 accesses to these regions are indeed safe.
1
1 If the input program contains a function declaration such as:
1
1 void foo (void);
1
1 then the implementation of 'foo' must allow 'j foo' and 'jal foo'
1 to be executed speculatively. GCC honors this restriction for
1 functions it compiles itself. It expects non-GCC functions (such
1 as hand-written assembly code) to do the same.
1
1 The option has three forms:
1
1 '-mr10k-cache-barrier=load-store'
1 Insert a cache barrier before a load or store that might be
1 speculatively executed and that might have side effects even
1 if aborted.
1
1 '-mr10k-cache-barrier=store'
1 Insert a cache barrier before a store that might be
1 speculatively executed and that might have side effects even
1 if aborted.
1
1 '-mr10k-cache-barrier=none'
1 Disable the insertion of cache barriers. This is the default
1 setting.
1
1 '-mflush-func=FUNC'
1 '-mno-flush-func'
1 Specifies the function to call to flush the I and D caches, or to
1 not call any such function. If called, the function must take the
1 same arguments as the common '_flush_func', that is, the address of
1 the memory range for which the cache is being flushed, the size of
1 the memory range, and the number 3 (to flush both caches). The
1 default depends on the target GCC was configured for, but commonly
1 is either '_flush_func' or '__cpu_flush'.
1
1 'mbranch-cost=NUM'
1 Set the cost of branches to roughly NUM "simple" instructions.
1 This cost is only a heuristic and is not guaranteed to produce
1 consistent results across releases. A zero cost redundantly
1 selects the default, which is based on the '-mtune' setting.
1
1 '-mbranch-likely'
1 '-mno-branch-likely'
1 Enable or disable use of Branch Likely instructions, regardless of
1 the default for the selected architecture. By default, Branch
1 Likely instructions may be generated if they are supported by the
1 selected architecture. An exception is for the MIPS32 and MIPS64
1 architectures and processors that implement those architectures;
1 for those, Branch Likely instructions are not be generated by
1 default because the MIPS32 and MIPS64 architectures specifically
1 deprecate their use.
1
1 '-mcompact-branches=never'
1 '-mcompact-branches=optimal'
1 '-mcompact-branches=always'
1 These options control which form of branches will be generated.
1 The default is '-mcompact-branches=optimal'.
1
1 The '-mcompact-branches=never' option ensures that compact branch
1 instructions will never be generated.
1
1 The '-mcompact-branches=always' option ensures that a compact
1 branch instruction will be generated if available. If a compact
1 branch instruction is not available, a delay slot form of the
1 branch will be used instead.
1
1 This option is supported from MIPS Release 6 onwards.
1
1 The '-mcompact-branches=optimal' option will cause a delay slot
1 branch to be used if one is available in the current ISA and the
1 delay slot is successfully filled. If the delay slot is not
1 filled, a compact branch will be chosen if one is available.
1
1 '-mfp-exceptions'
1 '-mno-fp-exceptions'
1 Specifies whether FP exceptions are enabled. This affects how FP
1 instructions are scheduled for some processors. The default is
1 that FP exceptions are enabled.
1
1 For instance, on the SB-1, if FP exceptions are disabled, and we
1 are emitting 64-bit code, then we can use both FP pipes.
1 Otherwise, we can only use one FP pipe.
1
1 '-mvr4130-align'
1 '-mno-vr4130-align'
1 The VR4130 pipeline is two-way superscalar, but can only issue two
1 instructions together if the first one is 8-byte aligned. When
1 this option is enabled, GCC aligns pairs of instructions that it
1 thinks should execute in parallel.
1
1 This option only has an effect when optimizing for the VR4130. It
1 normally makes code faster, but at the expense of making it bigger.
1 It is enabled by default at optimization level '-O3'.
1
1 '-msynci'
1 '-mno-synci'
1 Enable (disable) generation of 'synci' instructions on
1 architectures that support it. The 'synci' instructions (if
1 enabled) are generated when '__builtin___clear_cache' is compiled.
1
1 This option defaults to '-mno-synci', but the default can be
1 overridden by configuring GCC with '--with-synci'.
1
1 When compiling code for single processor systems, it is generally
1 safe to use 'synci'. However, on many multi-core (SMP) systems, it
1 does not invalidate the instruction caches on all cores and may
1 lead to undefined behavior.
1
1 '-mrelax-pic-calls'
1 '-mno-relax-pic-calls'
1 Try to turn PIC calls that are normally dispatched via register
1 '$25' into direct calls. This is only possible if the linker can
1 resolve the destination at link time and if the destination is
1 within range for a direct call.
1
1 '-mrelax-pic-calls' is the default if GCC was configured to use an
1 assembler and a linker that support the '.reloc' assembly directive
1 and '-mexplicit-relocs' is in effect. With '-mno-explicit-relocs',
1 this optimization can be performed by the assembler and the linker
1 alone without help from the compiler.
1
1 '-mmcount-ra-address'
1 '-mno-mcount-ra-address'
1 Emit (do not emit) code that allows '_mcount' to modify the calling
1 function's return address. When enabled, this option extends the
1 usual '_mcount' interface with a new RA-ADDRESS parameter, which
1 has type 'intptr_t *' and is passed in register '$12'. '_mcount'
1 can then modify the return address by doing both of the following:
1 * Returning the new address in register '$31'.
1 * Storing the new address in '*RA-ADDRESS', if RA-ADDRESS is
1 nonnull.
1
1 The default is '-mno-mcount-ra-address'.
1
1 '-mframe-header-opt'
1 '-mno-frame-header-opt'
1 Enable (disable) frame header optimization in the o32 ABI. When
1 using the o32 ABI, calling functions will allocate 16 bytes on the
1 stack for the called function to write out register arguments.
1 When enabled, this optimization will suppress the allocation of the
1 frame header if it can be determined that it is unused.
1
1 This optimization is off by default at all optimization levels.
1
1 '-mlxc1-sxc1'
1 '-mno-lxc1-sxc1'
1 When applicable, enable (disable) the generation of 'lwxc1',
1 'swxc1', 'ldxc1', 'sdxc1' instructions. Enabled by default.
1
1 '-mmadd4'
1 '-mno-madd4'
1 When applicable, enable (disable) the generation of 4-operand
1 'madd.s', 'madd.d' and related instructions. Enabled by default.
1