gcc: MIPS Paired-Single Support

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1 6.59.14 MIPS Paired-Single Support
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1 
1 The MIPS64 architecture includes a number of instructions that operate
1 on pairs of single-precision floating-point values.  Each pair is packed
1 into a 64-bit floating-point register, with one element being designated
1 the "upper half" and the other being designated the "lower half".
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1  GCC supports paired-single operations using both the generic vector
1 extensions (⇒Vector Extensions) and a collection of MIPS-specific
1 built-in functions.  Both kinds of support are enabled by the
1 '-mpaired-single' command-line option.
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1  The vector type associated with paired-single values is usually called
1 'v2sf'.  It can be defined in C as follows:
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1      typedef float v2sf __attribute__ ((vector_size (8)));
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1  'v2sf' values are initialized in the same way as aggregates.  For
1 example:
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1      v2sf a = {1.5, 9.1};
1      v2sf b;
1      float e, f;
1      b = (v2sf) {e, f};
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1  _Note:_ The CPU's endianness determines which value is stored in the
1 upper half of a register and which value is stored in the lower half.
1 On little-endian targets, the first value is the lower one and the
1 second value is the upper one.  The opposite order applies to big-endian
1 targets.  For example, the code above sets the lower half of 'a' to
1 '1.5' on little-endian targets and '9.1' on big-endian targets.
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