as: i386-Regs

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1 9.15.5 Register Naming
1 ----------------------
1 
1 Register operands are always prefixed with '%'.  The 80386 registers
1 consist of
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1    * the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx',
1      '%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the
1      stack pointer).
1 
1    * the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di',
1      '%si', '%bp', and '%sp'.
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1    * the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl',
1      '%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax',
1      '%bx', '%cx', and '%dx')
1 
1    * the 6 section registers '%cs' (code section), '%ds' (data section),
1      '%ss' (stack section), '%es', '%fs', and '%gs'.
1 
1    * the 5 processor control registers '%cr0', '%cr2', '%cr3', '%cr4',
1      and '%cr8'.
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1    * the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and
1      '%db7'.
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1    * the 2 test registers '%tr6' and '%tr7'.
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1    * the 8 floating point register stack '%st' or equivalently '%st(0)',
1      '%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and
1      '%st(7)'.  These registers are overloaded by 8 MMX registers
1      '%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'.
1 
1    * the 8 128-bit SSE registers registers '%xmm0', '%xmm1', '%xmm2',
1      '%xmm3', '%xmm4', '%xmm5', '%xmm6' and '%xmm7'.
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1    The AMD x86-64 architecture extends the register set by:
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1    * enhancing the 8 32-bit registers to 64-bit: '%rax' (the
1      accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the
1      frame pointer), '%rsp' (the stack pointer)
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1    * the 8 extended registers '%r8'-'%r15'.
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1    * the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d'.
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1    * the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w'.
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1    * the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b'.
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1    * the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'.
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1    * the 8 debug registers: '%db8'-'%db15'.
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1    * the 8 128-bit SSE registers: '%xmm8'-'%xmm15'.
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1    With the AVX extensions more registers were made available:
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1    * the 16 256-bit SSE '%ymm0'-'%ymm15' (only the first 8 available in
1      32-bit mode).  The bottom 128 bits are overlaid with the
1      'xmm0'-'xmm15' registers.
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1    The AVX2 extensions made in 64-bit mode more registers available:
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1    * the 16 128-bit registers '%xmm16'-'%xmm31' and the 16 256-bit
1      registers '%ymm16'-'%ymm31'.
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1    The AVX512 extensions added the following registers:
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1    * the 32 512-bit registers '%zmm0'-'%zmm31' (only the first 8
1      available in 32-bit mode).  The bottom 128 bits are overlaid with
1      the '%xmm0'-'%xmm31' registers and the first 256 bits are overlaid
1      with the '%ymm0'-'%ymm31' registers.
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1    * the 8 mask registers '%k0'-'%k7'.
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