as: i386-Mnemonics

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1 9.15.4 i386-Mnemonics
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1 9.15.4.1 Instruction Naming
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1 Instruction mnemonics are suffixed with one character modifiers which
1 specify the size of operands.  The letters 'b', 'w', 'l' and 'q' specify
1 byte, word, long and quadruple word operands.  If no suffix is specified
1 by an instruction then 'as' tries to fill in the missing suffix based on
1 the destination register operand (the last one by convention).  Thus,
1 'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is
1 equivalent to 'movw $1, bx'.  Note that this is incompatible with the
1 AT&T Unix assembler which assumes that a missing mnemonic suffix implies
1 long operand size.  (This incompatibility does not affect compiler
1 output since compilers always explicitly specify the mnemonic suffix.)
1 
1    Almost all instructions have the same names in AT&T and Intel format.
1 There are a few exceptions.  The sign extend and zero extend
1 instructions need two sizes to specify them.  They need a size to
1 sign/zero extend _from_ and a size to zero extend _to_.  This is
1 accomplished by using two instruction mnemonic suffixes in AT&T syntax.
1 Base names for sign extend and zero extend are 'movs...' and 'movz...'
1 in AT&T syntax ('movsx' and 'movzx' in Intel syntax).  The instruction
1 mnemonic suffixes are tacked on to this base name, the _from_ suffix
1 before the _to_ suffix.  Thus, 'movsbl %al, %edx' is AT&T syntax for
1 "move sign extend _from_ %al _to_ %edx."  Possible suffixes, thus, are
1 'bl' (from byte to long), 'bw' (from byte to word), 'wl' (from word to
1 long), 'bq' (from byte to quadruple word), 'wq' (from word to quadruple
1 word), and 'lq' (from long to quadruple word).
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1    Different encoding options can be specified via pseudo prefixes:
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1    * '{disp8}' - prefer 8-bit displacement.
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1    * '{disp32}' - prefer 32-bit displacement.
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1    * '{load}' - prefer load-form instruction.
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1    * '{store}' - prefer store-form instruction.
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1    * '{vex2}' - prefer 2-byte VEX prefix for VEX instruction.
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1    * '{vex3}' - prefer 3-byte VEX prefix for VEX instruction.
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1    * '{evex}' - encode with EVEX prefix.
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1    * '{rex}' - prefer REX prefix for integer and legacy vector
1      instructions (x86-64 only).  Note that this differs from the 'rex'
1      prefix which generates REX prefix unconditionally.
1 
1    * '{nooptimize}' - disable instruction size optimization.
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1    The Intel-syntax conversion instructions
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1    * 'cbw' -- sign-extend byte in '%al' to word in '%ax',
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1    * 'cwde' -- sign-extend word in '%ax' to long in '%eax',
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1    * 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax',
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1    * 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax',
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1    * 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64
1      only),
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1    * 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax'
1      (x86-64 only),
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1 are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T
1 naming.  'as' accepts either naming for these instructions.
1 
1    Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but
1 are 'call far' and 'jump far' in Intel convention.
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1 9.15.4.2 AT&T Mnemonic versus Intel Mnemonic
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1 'as' supports assembly using Intel mnemonic.  '.intel_mnemonic' selects
1 Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to
1 the usual AT&T mnemonic with AT&T syntax for compatibility with the
1 output of 'gcc'.  Several x87 instructions, 'fadd', 'fdiv', 'fdivp',
1 'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are
1 implemented in AT&T System V/386 assembler with different mnemonics from
1 those in Intel IA32 specification.  'gcc' generates those instructions
1 with AT&T mnemonic.
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