as: Compare-and-branch-i960

1 
1 9.17.4.2 Compare-and-Branch
1 ...........................
1 
1 The 960 architectures provide combined Compare-and-Branch instructions
1 that permit you to store the branch target in the lower 13 bits of the
1 instruction word itself.  However, if you specify a branch target far
1 enough away that its address won't fit in 13 bits, the assembler can
1 either issue an error, or convert your Compare-and-Branch instruction
1 into separate instructions to do the compare and the branch.
1 
1    Whether 'as' gives an error or expands the instruction depends on two
1 choices you can make: whether you use the '-no-relax' option, and
1 whether you use a "Compare and Branch" instruction or a "Compare and
1 Jump" instruction.  The "Jump" instructions are _always_ expanded if
1 necessary; the "Branch" instructions are expanded when necessary
1 _unless_ you specify '-no-relax'--in which case 'as' gives an error
1 instead.
1 
1    These are the Compare-and-Branch instructions, their "Jump" variants,
1 and the instruction pairs they may expand into:
1 
1              Compare and
1           Branch      Jump       Expanded to
1           ------    ------       ------------
1              bbc                 chkbit; bno
1              bbs                 chkbit; bo
1           cmpibe    cmpije       cmpi; be
1           cmpibg    cmpijg       cmpi; bg
1          cmpibge   cmpijge       cmpi; bge
1           cmpibl    cmpijl       cmpi; bl
1          cmpible   cmpijle       cmpi; ble
1          cmpibno   cmpijno       cmpi; bno
1          cmpibne   cmpijne       cmpi; bne
1           cmpibo    cmpijo       cmpi; bo
1           cmpobe    cmpoje       cmpo; be
1           cmpobg    cmpojg       cmpo; bg
1          cmpobge   cmpojge       cmpo; bge
1           cmpobl    cmpojl       cmpo; bl
1          cmpoble   cmpojle       cmpo; ble
1          cmpobne   cmpojne       cmpo; bne
1