as: ARM Opcodes
1
1 9.4.5 Opcodes
1 -------------
1
1 'as' implements all the standard ARM opcodes. It also implements
1 several pseudo opcodes, including several synthetic load instructions.
1
1 'NOP'
1 nop
1
1 This pseudo op will always evaluate to a legal ARM instruction that
1 does nothing. Currently it will evaluate to MOV r0, r0.
1
1 'LDR'
1 ldr <register> , = <expression>
1
1 If expression evaluates to a numeric constant then a MOV or MVN
1 instruction will be used in place of the LDR instruction, if the
1 constant can be generated by either of these instructions.
1 Otherwise the constant will be placed into the nearest literal pool
1 (if it not already there) and a PC relative LDR instruction will be
1 generated.
1
1 'ADR'
1 adr <register> <label>
1
1 This instruction will load the address of LABEL into the indicated
1 register. The instruction will evaluate to a PC relative ADD or
1 SUB instruction depending upon where the label is located. If the
1 label is out of range, or if it is not defined in the same file
1 (and section) as the ADR instruction, then an error will be
1 generated. This instruction will not make use of the literal pool.
1
1 'ADRL'
1 adrl <register> <label>
1
1 This instruction will load the address of LABEL into the indicated
1 register. The instruction will evaluate to one or two PC relative
1 ADD or SUB instructions depending upon where the label is located.
1 If a second instruction is not needed a NOP instruction will be
1 generated in its place, so that this instruction is always 8 bytes
1 long.
1
1 If the label is out of range, or if it is not defined in the same
1 file (and section) as the ADRL instruction, then an error will be
1 generated. This instruction will not make use of the literal pool.
1
1 For information on the ARM or Thumb instruction sets, see 'ARM
1 Software Development Toolkit Reference Manual', Advanced RISC Machines
1 Ltd.
1