as: ARM Directives
1
1 9.4.4 ARM Machine Directives
1 ----------------------------
1
1 '.align EXPRESSION [, EXPRESSION]'
1 This is the generic .ALIGN directive. For the ARM however if the
1 first argument is zero (ie no alignment is needed) the assembler
1 will behave as if the argument had been 2 (ie pad to the next four
1 byte boundary). This is for compatibility with ARM's own
1 assembler.
1
1 '.arch NAME'
1 Select the target architecture. Valid values for NAME are the same
1 as for the '-march' commandline option.
1
1 Specifying '.arch' clears any previously selected architecture
1 extensions.
1
1 '.arch_extension NAME'
1 Add or remove an architecture extension to the target architecture.
1 Valid values for NAME are the same as those accepted as
1 architectural extensions by the '-mcpu' commandline option.
1
1 '.arch_extension' may be used multiple times to add or remove
1 extensions incrementally to the architecture being compiled for.
1
1 '.arm'
1 This performs the same action as .CODE 32.
1
1 '.bss'
1 This directive switches to the '.bss' section.
1
1 '.cantunwind'
1 Prevents unwinding through the current function. No personality
1 routine or exception table data is required or permitted.
1
1 '.code [16|32]'
1 This directive selects the instruction set being generated. The
1 value 16 selects Thumb, with the value 32 selecting ARM.
1
1 '.cpu NAME'
1 Select the target processor. Valid values for NAME are the same as
1 for the '-mcpu' commandline option.
1
1 Specifying '.cpu' clears any previously selected architecture
1 extensions.
1
1 'NAME .dn REGISTER NAME [.TYPE] [[INDEX]]'
1 'NAME .qn REGISTER NAME [.TYPE] [[INDEX]]'
1
1 The 'dn' and 'qn' directives are used to create typed and/or
1 indexed register aliases for use in Advanced SIMD Extension (Neon)
1 instructions. The former should be used to create aliases of
1 double-precision registers, and the latter to create aliases of
1 quad-precision registers.
1
1 If these directives are used to create typed aliases, those aliases
1 can be used in Neon instructions instead of writing types after the
1 mnemonic or after each operand. For example:
1
1 x .dn d2.f32
1 y .dn d3.f32
1 z .dn d4.f32[1]
1 vmul x,y,z
1
1 This is equivalent to writing the following:
1
1 vmul.f32 d2,d3,d4[1]
1
1 Aliases created using 'dn' or 'qn' can be destroyed using 'unreq'.
1
1 '.eabi_attribute TAG, VALUE'
1 Set the EABI object attribute TAG to VALUE.
1
1 The TAG is either an attribute number, or one of the following:
1 'Tag_CPU_raw_name', 'Tag_CPU_name', 'Tag_CPU_arch',
1 'Tag_CPU_arch_profile', 'Tag_ARM_ISA_use', 'Tag_THUMB_ISA_use',
1 'Tag_FP_arch', 'Tag_WMMX_arch', 'Tag_Advanced_SIMD_arch',
1 'Tag_PCS_config', 'Tag_ABI_PCS_R9_use', 'Tag_ABI_PCS_RW_data',
1 'Tag_ABI_PCS_RO_data', 'Tag_ABI_PCS_GOT_use',
1 'Tag_ABI_PCS_wchar_t', 'Tag_ABI_FP_rounding',
1 'Tag_ABI_FP_denormal', 'Tag_ABI_FP_exceptions',
1 'Tag_ABI_FP_user_exceptions', 'Tag_ABI_FP_number_model',
1 'Tag_ABI_align_needed', 'Tag_ABI_align_preserved',
1 'Tag_ABI_enum_size', 'Tag_ABI_HardFP_use', 'Tag_ABI_VFP_args',
1 'Tag_ABI_WMMX_args', 'Tag_ABI_optimization_goals',
1 'Tag_ABI_FP_optimization_goals', 'Tag_compatibility',
1 'Tag_CPU_unaligned_access', 'Tag_FP_HP_extension',
1 'Tag_ABI_FP_16bit_format', 'Tag_MPextension_use', 'Tag_DIV_use',
1 'Tag_nodefaults', 'Tag_also_compatible_with', 'Tag_conformance',
1 'Tag_T2EE_use', 'Tag_Virtualization_use'
1
1 The VALUE is either a 'number', '"string"', or 'number, "string"'
1 depending on the tag.
1
1 Note - the following legacy values are also accepted by TAG:
1 'Tag_VFP_arch', 'Tag_ABI_align8_needed',
1 'Tag_ABI_align8_preserved', 'Tag_VFP_HP_extension',
1
1 '.even'
1 This directive aligns to an even-numbered address.
1
1 '.extend EXPRESSION [, EXPRESSION]*'
1 '.ldouble EXPRESSION [, EXPRESSION]*'
1 These directives write 12byte long double floating-point values to
1 the output section. These are not compatible with current ARM
1 processors or ABIs.
1
1 '.fnend'
1 Marks the end of a function with an unwind table entry. The unwind
1 index table entry is created when this directive is processed.
1
1 If no personality routine has been specified then standard
1 personality routine 0 or 1 will be used, depending on the number of
1 unwind opcodes required.
1
1 '.fnstart'
1 Marks the start of a function with an unwind table entry.
1
1 '.force_thumb'
1 This directive forces the selection of Thumb instructions, even if
1 the target processor does not support those instructions
1
1 '.fpu NAME'
1 Select the floating-point unit to assemble for. Valid values for
1 NAME are the same as for the '-mfpu' commandline option.
1
1 '.handlerdata'
1 Marks the end of the current function, and the start of the
1 exception table entry for that function. Anything between this
1 directive and the '.fnend' directive will be added to the exception
1 table entry.
1
1 Must be preceded by a '.personality' or '.personalityindex'
1 directive.
1
1 '.inst OPCODE [ , ... ]'
1 '.inst.n OPCODE [ , ... ]'
1 '.inst.w OPCODE [ , ... ]'
1 Generates the instruction corresponding to the numerical value
1 OPCODE. '.inst.n' and '.inst.w' allow the Thumb instruction size
1 to be specified explicitly, overriding the normal encoding rules.
1
1 '.ldouble EXPRESSION [, EXPRESSION]*'
1 See '.extend'.
1
1 '.ltorg'
1 This directive causes the current contents of the literal pool to
1 be dumped into the current section (which is assumed to be the
1 .text section) at the current location (aligned to a word
1 boundary). 'GAS' maintains a separate literal pool for each
1 section and each sub-section. The '.ltorg' directive will only
1 affect the literal pool of the current section and sub-section. At
1 the end of assembly all remaining, un-empty literal pools will
1 automatically be dumped.
1
1 Note - older versions of 'GAS' would dump the current literal pool
1 any time a section change occurred. This is no longer done, since
1 it prevents accurate control of the placement of literal pools.
1
1 '.movsp REG [, #OFFSET]'
1 Tell the unwinder that REG contains an offset from the current
1 stack pointer. If OFFSET is not specified then it is assumed to be
1 zero.
1
1 '.object_arch NAME'
1 Override the architecture recorded in the EABI object attribute
1 section. Valid values for NAME are the same as for the '.arch'
1 directive. Typically this is useful when code uses runtime
1 detection of CPU features.
1
1 '.packed EXPRESSION [, EXPRESSION]*'
1 This directive writes 12-byte packed floating-point values to the
1 output section. These are not compatible with current ARM
1 processors or ABIs.
1
1 '.pad #COUNT'
1 Generate unwinder annotations for a stack adjustment of COUNT
1 bytes. A positive value indicates the function prologue allocated
1 stack space by decrementing the stack pointer.
1
1 '.personality NAME'
1 Sets the personality routine for the current function to NAME.
1
1 '.personalityindex INDEX'
1 Sets the personality routine for the current function to the EABI
1 standard routine number INDEX
1
1 '.pool'
1 This is a synonym for .ltorg.
1
1 'NAME .req REGISTER NAME'
1 This creates an alias for REGISTER NAME called NAME. For example:
1
1 foo .req r0
1
1 '.save REGLIST'
1 Generate unwinder annotations to restore the registers in REGLIST.
1 The format of REGLIST is the same as the corresponding
1 store-multiple instruction.
1
1 _core registers_
1 .save {r4, r5, r6, lr}
1 stmfd sp!, {r4, r5, r6, lr}
1 _FPA registers_
1 .save f4, 2
1 sfmfd f4, 2, [sp]!
1 _VFP registers_
1 .save {d8, d9, d10}
1 fstmdx sp!, {d8, d9, d10}
1 _iWMMXt registers_
1 .save {wr10, wr11}
1 wstrd wr11, [sp, #-8]!
1 wstrd wr10, [sp, #-8]!
1 or
1 .save wr11
1 wstrd wr11, [sp, #-8]!
1 .save wr10
1 wstrd wr10, [sp, #-8]!
1
1 '.setfp FPREG, SPREG [, #OFFSET]'
1 Make all unwinder annotations relative to a frame pointer. Without
1 this the unwinder will use offsets from the stack pointer.
1
1 The syntax of this directive is the same as the 'add' or 'mov'
1 instruction used to set the frame pointer. SPREG must be either
1 'sp' or mentioned in a previous '.movsp' directive.
1
1 .movsp ip
1 mov ip, sp
1 ...
1 .setfp fp, ip, #4
1 add fp, ip, #4
1
1 '.secrel32 EXPRESSION [, EXPRESSION]*'
1 This directive emits relocations that evaluate to the
1 section-relative offset of each expression's symbol. This
1 directive is only supported for PE targets.
1
1 '.syntax [unified | divided]'
1 This directive sets the Instruction Set Syntax as described in the
1 ⇒ARM-Instruction-Set section.
1
1 '.thumb'
1 This performs the same action as .CODE 16.
1
1 '.thumb_func'
1 This directive specifies that the following symbol is the name of a
1 Thumb encoded function. This information is necessary in order to
1 allow the assembler and linker to generate correct code for
1 interworking between Arm and Thumb instructions and should be used
1 even if interworking is not going to be performed. The presence of
1 this directive also implies '.thumb'
1
1 This directive is not necessary when generating EABI objects. On
1 these targets the encoding is implicit when generating Thumb code.
1
1 '.thumb_set'
1 This performs the equivalent of a '.set' directive in that it
1 creates a symbol which is an alias for another symbol (possibly not
1 yet defined). This directive also has the added property in that
1 it marks the aliased symbol as being a thumb function entry point,
1 in the same way that the '.thumb_func' directive does.
1
1 '.tlsdescseq TLS-VARIABLE'
1 This directive is used to annotate parts of an inlined TLS
1 descriptor trampoline. Normally the trampoline is provided by the
1 linker, and this directive is not needed.
1
1 '.unreq ALIAS-NAME'
1 This undefines a register alias which was previously defined using
1 the 'req', 'dn' or 'qn' directives. For example:
1
1 foo .req r0
1 .unreq foo
1
1 An error occurs if the name is undefined. Note - this pseudo op
1 can be used to delete builtin in register name aliases (eg 'r0').
1 This should only be done if it is really necessary.
1
1 '.unwind_raw OFFSET, BYTE1, ...'
1 Insert one of more arbitrary unwind opcode bytes, which are known
1 to adjust the stack pointer by OFFSET bytes.
1
1 For example '.unwind_raw 4, 0xb1, 0x01' is equivalent to '.save
1 {r0}'
1
1 '.vsave VFP-REGLIST'
1 Generate unwinder annotations to restore the VFP registers in
1 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to
1 be restored using VLDM. The format of VFP-REGLIST is the same as
1 the corresponding store-multiple instruction.
1
1 _VFP registers_
1 .vsave {d8, d9, d10}
1 fstmdd sp!, {d8, d9, d10}
1 _VFPv3 registers_
1 .vsave {d15, d16, d17}
1 vstm sp!, {d15, d16, d17}
1
1 Since FLDMX and FSTMX are now deprecated, this directive should be
1 used in favour of '.save' for saving VFP registers for ARMv6 and
1 above.
1