make: Overriding Makefiles
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1 3.6 Overriding Part of Another Makefile
1 =======================================
1
1 Sometimes it is useful to have a makefile that is mostly just like
1 another makefile. You can often use the 'include' directive to include
1 one in the other, and add more targets or variable definitions.
1 However, it is invalid for two makefiles to give different recipes for
1 the same target. But there is another way.
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1 In the containing makefile (the one that wants to include the other),
1 you can use a match-anything pattern rule to say that to remake any
1 target that cannot be made from the information in the containing
11 makefile, 'make' should look in another makefile. ⇒Pattern
Rules, for more information on pattern rules.
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1 For example, if you have a makefile called 'Makefile' that says how
1 to make the target 'foo' (and other targets), you can write a makefile
1 called 'GNUmakefile' that contains:
1
1 foo:
1 frobnicate > foo
1
1 %: force
1 @$(MAKE) -f Makefile $@
1 force: ;
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1 If you say 'make foo', 'make' will find 'GNUmakefile', read it, and
1 see that to make 'foo', it needs to run the recipe 'frobnicate > foo'.
1 If you say 'make bar', 'make' will find no way to make 'bar' in
1 'GNUmakefile', so it will use the recipe from the pattern rule: 'make -f
1 Makefile bar'. If 'Makefile' provides a rule for updating 'bar', 'make'
1 will apply the rule. And likewise for any other target that
1 'GNUmakefile' does not say how to make.
1
1 The way this works is that the pattern rule has a pattern of just
1 '%', so it matches any target whatever. The rule specifies a
1 prerequisite 'force', to guarantee that the recipe will be run even if
1 the target file already exists. We give the 'force' target an empty
1 recipe to prevent 'make' from searching for an implicit rule to build
1 it--otherwise it would apply the same match-anything rule to 'force'
1 itself and create a prerequisite loop!
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