ld: ARM

1 
1 4.4 'ld' and the ARM family
1 ===========================
1 
1 For the ARM, 'ld' will generate code stubs to allow functions calls
1 between ARM and Thumb code.  These stubs only work with code that has
1 been compiled and assembled with the '-mthumb-interwork' command line
1 option.  If it is necessary to link with old ARM object files or
1 libraries, which have not been compiled with the -mthumb-interwork
1 option then the '--support-old-code' command line switch should be given
1 to the linker.  This will make it generate larger stub functions which
1 will work with non-interworking aware ARM code.  Note, however, the
1 linker does not support generating stubs for function calls to
1 non-interworking aware Thumb code.
1 
1    The '--thumb-entry' switch is a duplicate of the generic '--entry'
1 switch, in that it sets the program's starting address.  But it also
1 sets the bottom bit of the address, so that it can be branched to using
1 a BX instruction, and the program will start executing in Thumb mode
1 straight away.
1 
1    The '--use-nul-prefixed-import-tables' switch is specifying, that the
1 import tables idata4 and idata5 have to be generated with a zero element
1 prefix for import libraries.  This is the old style to generate import
1 tables.  By default this option is turned off.
1 
1    The '--be8' switch instructs 'ld' to generate BE8 format executables.
1 This option is only valid when linking big-endian objects - ie ones
1 which have been assembled with the '-EB' option.  The resulting image
1 will contain big-endian data and little-endian code.
1 
1    The 'R_ARM_TARGET1' relocation is typically used for entries in the
1 '.init_array' section.  It is interpreted as either 'R_ARM_REL32' or
1 'R_ARM_ABS32', depending on the target.  The '--target1-rel' and
1 '--target1-abs' switches override the default.
1 
1    The '--target2=type' switch overrides the default definition of the
1 'R_ARM_TARGET2' relocation.  Valid values for 'type', their meanings,
1 and target defaults are as follows:
1 'rel'
1      'R_ARM_REL32' (arm*-*-elf, arm*-*-eabi)
1 'abs'
1      'R_ARM_ABS32' (arm*-*-symbianelf)
1 'got-rel'
1      'R_ARM_GOT_PREL' (arm*-*-linux, arm*-*-*bsd)
1 
1    The 'R_ARM_V4BX' relocation (defined by the ARM AAELF specification)
1 enables objects compiled for the ARMv4 architecture to be
1 interworking-safe when linked with other objects compiled for ARMv4t,
1 but also allows pure ARMv4 binaries to be built from the same ARMv4
1 objects.
1 
1    In the latter case, the switch '--fix-v4bx' must be passed to the
1 linker, which causes v4t 'BX rM' instructions to be rewritten as 'MOV
1 PC,rM', since v4 processors do not have a 'BX' instruction.
1 
1    In the former case, the switch should not be used, and 'R_ARM_V4BX'
1 relocations are ignored.
1 
1    Replace 'BX rM' instructions identified by 'R_ARM_V4BX' relocations
1 with a branch to the following veneer:
1 
1      TST rM, #1
1      MOVEQ PC, rM
1      BX Rn
1 
1    This allows generation of libraries/applications that work on ARMv4
1 cores and are still interworking safe.  Note that the above veneer
1 clobbers the condition flags, so may cause incorrect program behavior in
1 rare cases.
1 
1    The '--use-blx' switch enables the linker to use ARM/Thumb BLX
1 instructions (available on ARMv5t and above) in various situations.
1 Currently it is used to perform calls via the PLT from Thumb code using
1 BLX rather than using BX and a mode-switching stub before each PLT
1 entry.  This should lead to such calls executing slightly faster.
1 
1    This option is enabled implicitly for SymbianOS, so there is no need
1 to specify it if you are using that target.
1 
1    The '--vfp11-denorm-fix' switch enables a link-time workaround for a
1 bug in certain VFP11 coprocessor hardware, which sometimes allows
1 instructions with denorm operands (which must be handled by support
1 code) to have those operands overwritten by subsequent instructions
1 before the support code can read the intended values.
1 
1    The bug may be avoided in scalar mode if you allow at least one
1 intervening instruction between a VFP11 instruction which uses a
1 register and another instruction which writes to the same register, or
1 at least two intervening instructions if vector mode is in use.  The bug
1 only affects full-compliance floating-point mode: you do not need this
1 workaround if you are using "runfast" mode.  Please contact ARM for
1 further details.
1 
1    If you know you are using buggy VFP11 hardware, you can enable this
1 workaround by specifying the linker option '--vfp-denorm-fix=scalar' if
1 you are using the VFP11 scalar mode only, or '--vfp-denorm-fix=vector'
1 if you are using vector mode (the latter also works for scalar code).
1 The default is '--vfp-denorm-fix=none'.
1 
1    If the workaround is enabled, instructions are scanned for
1 potentially-troublesome sequences, and a veneer is created for each such
1 sequence which may trigger the erratum.  The veneer consists of the
1 first instruction of the sequence and a branch back to the subsequent
1 instruction.  The original instruction is then replaced with a branch to
1 the veneer.  The extra cycles required to call and return from the
1 veneer are sufficient to avoid the erratum in both the scalar and vector
1 cases.
1 
1    The '--fix-arm1176' switch enables a link-time workaround for an
1 erratum in certain ARM1176 processors.  The workaround is enabled by
1 default if you are targeting ARM v6 (excluding ARM v6T2) or earlier.  It
1 can be disabled unconditionally by specifying '--no-fix-arm1176'.
1 
1    Further information is available in the "ARM1176JZ-S and ARM1176JZF-S
1 Programmer Advice Notice" available on the ARM documentation website at:
1 http://infocenter.arm.com/.
1 
1    The '--fix-stm32l4xx-629360' switch enables a link-time workaround
1 for a bug in the bus matrix / memory controller for some of the STM32
1 Cortex-M4 based products (STM32L4xx).  When accessing off-chip memory
1 via the affected bus for bus reads of 9 words or more, the bus can
1 generate corrupt data and/or abort.  These are only core-initiated
1 accesses (not DMA), and might affect any access: integer loads such as
1 LDM, POP and floating-point loads such as VLDM, VPOP. Stores are not
1 affected.
1 
1    The bug can be avoided by splitting memory accesses into the
1 necessary chunks to keep bus reads below 8 words.
1 
1    The workaround is not enabled by default, this is equivalent to use
1 '--fix-stm32l4xx-629360=none'.  If you know you are using buggy
1 STM32L4xx hardware, you can enable the workaround by specifying the
1 linker option '--fix-stm32l4xx-629360', or the equivalent
1 '--fix-stm32l4xx-629360=default'.
1 
1    If the workaround is enabled, instructions are scanned for
1 potentially-troublesome sequences, and a veneer is created for each such
1 sequence which may trigger the erratum.  The veneer consists in a
1 replacement sequence emulating the behaviour of the original one and a
1 branch back to the subsequent instruction.  The original instruction is
1 then replaced with a branch to the veneer.
1 
1    The workaround does not always preserve the memory access order for
1 the LDMDB instruction, when the instruction loads the PC.
1 
1    The workaround is not able to handle problematic instructions when
1 they are in the middle of an IT block, since a branch is not allowed
1 there.  In that case, the linker reports a warning and no replacement
1 occurs.
1 
1    The workaround is not able to replace problematic instructions with a
1 PC-relative branch instruction if the '.text' section is too large.  In
1 that case, when the branch that replaces the original code cannot be
1 encoded, the linker reports a warning and no replacement occurs.
1 
1    The '--no-enum-size-warning' switch prevents the linker from warning
1 when linking object files that specify incompatible EABI enumeration
1 size attributes.  For example, with this switch enabled, linking of an
1 object file using 32-bit enumeration values with another using
1 enumeration values fitted into the smallest possible space will not be
1 diagnosed.
1 
1    The '--no-wchar-size-warning' switch prevents the linker from warning
1 when linking object files that specify incompatible EABI 'wchar_t' size
1 attributes.  For example, with this switch enabled, linking of an object
1 file using 32-bit 'wchar_t' values with another using 16-bit 'wchar_t'
1 values will not be diagnosed.
1 
1    The '--pic-veneer' switch makes the linker use PIC sequences for
1 ARM/Thumb interworking veneers, even if the rest of the binary is not
1 PIC. This avoids problems on uClinux targets where '--emit-relocs' is
1 used to generate relocatable binaries.
1 
1    The linker will automatically generate and insert small sequences of
1 code into a linked ARM ELF executable whenever an attempt is made to
1 perform a function call to a symbol that is too far away.  The placement
1 of these sequences of instructions - called stubs - is controlled by the
1 command line option '--stub-group-size=N'.  The placement is important
1 because a poor choice can create a need for duplicate stubs, increasing
1 the code size.  The linker will try to group stubs together in order to
1 reduce interruptions to the flow of code, but it needs guidance as to
1 how big these groups should be and where they should be placed.
1 
1    The value of 'N', the parameter to the '--stub-group-size=' option
1 controls where the stub groups are placed.  If it is negative then all
1 stubs are placed after the first branch that needs them.  If it is
1 positive then the stubs can be placed either before or after the
1 branches that need them.  If the value of 'N' is 1 (either +1 or -1)
1 then the linker will choose exactly where to place groups of stubs,
1 using its built in heuristics.  A value of 'N' greater than 1 (or
1 smaller than -1) tells the linker that a single group of stubs can
1 service at most 'N' bytes from the input sections.
1 
1    The default, if '--stub-group-size=' is not specified, is 'N = +1'.
1 
1    Farcalls stubs insertion is fully supported for the ARM-EABI target
1 only, because it relies on object files properties not present
1 otherwise.
1 
1    The '--fix-cortex-a8' switch enables a link-time workaround for an
1 erratum in certain Cortex-A8 processors.  The workaround is enabled by
1 default if you are targeting the ARM v7-A architecture profile.  It can
1 be enabled otherwise by specifying '--fix-cortex-a8', or disabled
1 unconditionally by specifying '--no-fix-cortex-a8'.
1 
1    The erratum only affects Thumb-2 code.  Please contact ARM for
1 further details.
1 
1    The '--fix-cortex-a53-835769' switch enables a link-time workaround
1 for erratum 835769 present on certain early revisions of Cortex-A53
1 processors.  The workaround is disabled by default.  It can be enabled
1 by specifying '--fix-cortex-a53-835769', or disabled unconditionally by
1 specifying '--no-fix-cortex-a53-835769'.
1 
1    Please contact ARM for further details.
1 
1    The '--no-merge-exidx-entries' switch disables the merging of
1 adjacent exidx entries in debuginfo.
1 
1    The '--long-plt' option enables the use of 16 byte PLT entries which
1 support up to 4Gb of code.  The default is to use 12 byte PLT entries
1 which only support 512Mb of code.
1 
1    The '--no-apply-dynamic-relocs' option makes AArch64 linker do not
1 apply link-time values for dynamic relocations.
1 
1    All SG veneers are placed in the special output section
1 '.gnu.sgstubs'.  Its start address must be set, either with the command
1 line option '--section-start' or in a linker script, to indicate where
1 to place these veneers in memory.
1 
1    The '--cmse-implib' option requests that the import libraries
1 specified by the '--out-implib' and '--in-implib' options are secure
1 gateway import libraries, suitable for linking a non-secure executable
1 against secure code as per ARMv8-M Security Extensions.
1 
1    The '--in-implib=file' specifies an input import library whose
1 symbols must keep the same address in the executable being produced.  A
1 warning is given if no '--out-implib' is given but new symbols have been
1 introduced in the executable that should be listed in its import
1 library.  Otherwise, if '--out-implib' is specified, the symbols are
1 added to the output import library.  A warning is also given if some
1 symbols present in the input import library have disappeared from the
1 executable.  This option is only effective for Secure Gateway import
1 libraries, ie.  when '--cmse-implib' is specified.
1