gccint: MIPS Coprocessors
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1 18.26 Defining coprocessor specifics for MIPS targets.
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1 The MIPS specification allows MIPS implementations to have as many as 4
1 coprocessors, each with as many as 32 private registers. GCC supports
1 accessing these registers and transferring values between the registers
1 and memory using asm-ized variables. For example:
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1 register unsigned int cp0count asm ("c0r1");
1 unsigned int d;
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1 d = cp0count + 3;
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1 ("c0r1" is the default name of register 1 in coprocessor 0; alternate
1 names may be added as described below, or the default names may be
1 overridden entirely in 'SUBTARGET_CONDITIONAL_REGISTER_USAGE'.)
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1 Coprocessor registers are assumed to be epilogue-used; sets to them
1 will be preserved even if it does not appear that the register is used
1 again later in the function.
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1 Another note: according to the MIPS spec, coprocessor 1 (if present) is
1 the FPU. One accesses COP1 registers through standard mips
1 floating-point support; they are not included in this mechanism.
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