gcc: x86 specific memory model extensions for transactional memory
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1 6.55 x86-Specific Memory Model Extensions for Transactional Memory
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1 The x86 architecture supports additional memory ordering flags to mark
1 critical sections for hardware lock elision. These must be specified in
1 addition to an existing memory order to atomic intrinsics.
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1 '__ATOMIC_HLE_ACQUIRE'
1 Start lock elision on a lock variable. Memory order must be
1 '__ATOMIC_ACQUIRE' or stronger.
1 '__ATOMIC_HLE_RELEASE'
1 End lock elision on a lock variable. Memory order must be
1 '__ATOMIC_RELEASE' or stronger.
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1 When a lock acquire fails, it is required for good performance to abort
1 the transaction quickly. This can be done with a '_mm_pause'.
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1 #include <immintrin.h> // For _mm_pause
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1 int lockvar;
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1 /* Acquire lock with lock elision */
1 while (__atomic_exchange_n(&lockvar, 1, __ATOMIC_ACQUIRE|__ATOMIC_HLE_ACQUIRE))
1 _mm_pause(); /* Abort failed transaction */
1 ...
1 /* Free lock with lock elision */
1 __atomic_store_n(&lockvar, 0, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE);
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