gcc: Visium Options
1
1 3.18.53 Visium Options
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1
1 '-mdebug'
1 A program which performs file I/O and is destined to run on an MCM
1 target should be linked with this option. It causes the libraries
1 libc.a and libdebug.a to be linked. The program should be run on
1 the target under the control of the GDB remote debugging stub.
1
1 '-msim'
1 A program which performs file I/O and is destined to run on the
1 simulator should be linked with option. This causes libraries
1 libc.a and libsim.a to be linked.
1
1 '-mfpu'
1 '-mhard-float'
1 Generate code containing floating-point instructions. This is the
1 default.
1
1 '-mno-fpu'
1 '-msoft-float'
1 Generate code containing library calls for floating-point.
1
1 '-msoft-float' changes the calling convention in the output file;
1 therefore, it is only useful if you compile _all_ of a program with
1 this option. In particular, you need to compile 'libgcc.a', the
1 library that comes with GCC, with '-msoft-float' in order for this
1 to work.
1
1 '-mcpu=CPU_TYPE'
1 Set the instruction set, register set, and instruction scheduling
1 parameters for machine type CPU_TYPE. Supported values for
1 CPU_TYPE are 'mcm', 'gr5' and 'gr6'.
1
1 'mcm' is a synonym of 'gr5' present for backward compatibility.
1
1 By default (unless configured otherwise), GCC generates code for
1 the GR5 variant of the Visium architecture.
1
1 With '-mcpu=gr6', GCC generates code for the GR6 variant of the
1 Visium architecture. The only difference from GR5 code is that the
1 compiler will generate block move instructions.
1
1 '-mtune=CPU_TYPE'
1 Set the instruction scheduling parameters for machine type
1 CPU_TYPE, but do not set the instruction set or register set that
1 the option '-mcpu=CPU_TYPE' would.
1
1 '-msv-mode'
1 Generate code for the supervisor mode, where there are no
1 restrictions on the access to general registers. This is the
1 default.
1
1 '-muser-mode'
1 Generate code for the user mode, where the access to some general
1 registers is forbidden: on the GR5, registers r24 to r31 cannot be
1 accessed in this mode; on the GR6, only registers r29 to r31 are
1 affected.
1