gcc: SH Options
1
1 3.18.44 SH Options
1 ------------------
1
1 These '-m' options are defined for the SH implementations:
1
1 '-m1'
1 Generate code for the SH1.
1
1 '-m2'
1 Generate code for the SH2.
1
1 '-m2e'
1 Generate code for the SH2e.
1
1 '-m2a-nofpu'
1 Generate code for the SH2a without FPU, or for a SH2a-FPU in such a
1 way that the floating-point unit is not used.
1
1 '-m2a-single-only'
1 Generate code for the SH2a-FPU, in such a way that no
1 double-precision floating-point operations are used.
1
1 '-m2a-single'
1 Generate code for the SH2a-FPU assuming the floating-point unit is
1 in single-precision mode by default.
1
1 '-m2a'
1 Generate code for the SH2a-FPU assuming the floating-point unit is
1 in double-precision mode by default.
1
1 '-m3'
1 Generate code for the SH3.
1
1 '-m3e'
1 Generate code for the SH3e.
1
1 '-m4-nofpu'
1 Generate code for the SH4 without a floating-point unit.
1
1 '-m4-single-only'
1 Generate code for the SH4 with a floating-point unit that only
1 supports single-precision arithmetic.
1
1 '-m4-single'
1 Generate code for the SH4 assuming the floating-point unit is in
1 single-precision mode by default.
1
1 '-m4'
1 Generate code for the SH4.
1
1 '-m4-100'
1 Generate code for SH4-100.
1
1 '-m4-100-nofpu'
1 Generate code for SH4-100 in such a way that the floating-point
1 unit is not used.
1
1 '-m4-100-single'
1 Generate code for SH4-100 assuming the floating-point unit is in
1 single-precision mode by default.
1
1 '-m4-100-single-only'
1 Generate code for SH4-100 in such a way that no double-precision
1 floating-point operations are used.
1
1 '-m4-200'
1 Generate code for SH4-200.
1
1 '-m4-200-nofpu'
1 Generate code for SH4-200 without in such a way that the
1 floating-point unit is not used.
1
1 '-m4-200-single'
1 Generate code for SH4-200 assuming the floating-point unit is in
1 single-precision mode by default.
1
1 '-m4-200-single-only'
1 Generate code for SH4-200 in such a way that no double-precision
1 floating-point operations are used.
1
1 '-m4-300'
1 Generate code for SH4-300.
1
1 '-m4-300-nofpu'
1 Generate code for SH4-300 without in such a way that the
1 floating-point unit is not used.
1
1 '-m4-300-single'
1 Generate code for SH4-300 in such a way that no double-precision
1 floating-point operations are used.
1
1 '-m4-300-single-only'
1 Generate code for SH4-300 in such a way that no double-precision
1 floating-point operations are used.
1
1 '-m4-340'
1 Generate code for SH4-340 (no MMU, no FPU).
1
1 '-m4-500'
1 Generate code for SH4-500 (no FPU). Passes '-isa=sh4-nofpu' to the
1 assembler.
1
1 '-m4a-nofpu'
1 Generate code for the SH4al-dsp, or for a SH4a in such a way that
1 the floating-point unit is not used.
1
1 '-m4a-single-only'
1 Generate code for the SH4a, in such a way that no double-precision
1 floating-point operations are used.
1
1 '-m4a-single'
1 Generate code for the SH4a assuming the floating-point unit is in
1 single-precision mode by default.
1
1 '-m4a'
1 Generate code for the SH4a.
1
1 '-m4al'
1 Same as '-m4a-nofpu', except that it implicitly passes '-dsp' to
1 the assembler. GCC doesn't generate any DSP instructions at the
1 moment.
1
1 '-mb'
1 Compile code for the processor in big-endian mode.
1
1 '-ml'
1 Compile code for the processor in little-endian mode.
1
1 '-mdalign'
1 Align doubles at 64-bit boundaries. Note that this changes the
1 calling conventions, and thus some functions from the standard C
1 library do not work unless you recompile it first with '-mdalign'.
1
1 '-mrelax'
1 Shorten some address references at link time, when possible; uses
1 the linker option '-relax'.
1
1 '-mbigtable'
1 Use 32-bit offsets in 'switch' tables. The default is to use
1 16-bit offsets.
1
1 '-mbitops'
1 Enable the use of bit manipulation instructions on SH2A.
1
1 '-mfmovd'
1 Enable the use of the instruction 'fmovd'. Check '-mdalign' for
1 alignment constraints.
1
1 '-mrenesas'
1 Comply with the calling conventions defined by Renesas.
1
1 '-mno-renesas'
1 Comply with the calling conventions defined for GCC before the
1 Renesas conventions were available. This option is the default for
1 all targets of the SH toolchain.
1
1 '-mnomacsave'
1 Mark the 'MAC' register as call-clobbered, even if '-mrenesas' is
1 given.
1
1 '-mieee'
1 '-mno-ieee'
1 Control the IEEE compliance of floating-point comparisons, which
1 affects the handling of cases where the result of a comparison is
1 unordered. By default '-mieee' is implicitly enabled. If
1 '-ffinite-math-only' is enabled '-mno-ieee' is implicitly set,
1 which results in faster floating-point greater-equal and less-equal
1 comparisons. The implicit settings can be overridden by specifying
1 either '-mieee' or '-mno-ieee'.
1
1 '-minline-ic_invalidate'
1 Inline code to invalidate instruction cache entries after setting
1 up nested function trampolines. This option has no effect if
1 '-musermode' is in effect and the selected code generation option
1 (e.g. '-m4') does not allow the use of the 'icbi' instruction. If
1 the selected code generation option does not allow the use of the
1 'icbi' instruction, and '-musermode' is not in effect, the inlined
1 code manipulates the instruction cache address array directly with
1 an associative write. This not only requires privileged mode at
1 run time, but it also fails if the cache line had been mapped via
1 the TLB and has become unmapped.
1
1 '-misize'
1 Dump instruction size and location in the assembly code.
1
1 '-mpadstruct'
1 This option is deprecated. It pads structures to multiple of 4
1 bytes, which is incompatible with the SH ABI.
1
1 '-matomic-model=MODEL'
1 Sets the model of atomic operations and additional parameters as a
1 comma separated list. For details on the atomic built-in functions
1 see ⇒__atomic Builtins. The following models and parameters
1 are supported:
1
1 'none'
1 Disable compiler generated atomic sequences and emit library
1 calls for atomic operations. This is the default if the
1 target is not 'sh*-*-linux*'.
1
1 'soft-gusa'
1 Generate GNU/Linux compatible gUSA software atomic sequences
1 for the atomic built-in functions. The generated atomic
1 sequences require additional support from the
1 interrupt/exception handling code of the system and are only
1 suitable for SH3* and SH4* single-core systems. This option
1 is enabled by default when the target is 'sh*-*-linux*' and
1 SH3* or SH4*. When the target is SH4A, this option also
1 partially utilizes the hardware atomic instructions 'movli.l'
1 and 'movco.l' to create more efficient code, unless 'strict'
1 is specified.
1
1 'soft-tcb'
1 Generate software atomic sequences that use a variable in the
1 thread control block. This is a variation of the gUSA
1 sequences which can also be used on SH1* and SH2* targets.
1 The generated atomic sequences require additional support from
1 the interrupt/exception handling code of the system and are
1 only suitable for single-core systems. When using this model,
1 the 'gbr-offset=' parameter has to be specified as well.
1
1 'soft-imask'
1 Generate software atomic sequences that temporarily disable
1 interrupts by setting 'SR.IMASK = 1111'. This model works
1 only when the program runs in privileged mode and is only
1 suitable for single-core systems. Additional support from the
1 interrupt/exception handling code of the system is not
1 required. This model is enabled by default when the target is
1 'sh*-*-linux*' and SH1* or SH2*.
1
1 'hard-llcs'
1 Generate hardware atomic sequences using the 'movli.l' and
1 'movco.l' instructions only. This is only available on SH4A
1 and is suitable for multi-core systems. Since the hardware
1 instructions support only 32 bit atomic variables access to 8
1 or 16 bit variables is emulated with 32 bit accesses. Code
1 compiled with this option is also compatible with other
1 software atomic model interrupt/exception handling systems if
1 executed on an SH4A system. Additional support from the
1 interrupt/exception handling code of the system is not
1 required for this model.
1
1 'gbr-offset='
1 This parameter specifies the offset in bytes of the variable
1 in the thread control block structure that should be used by
1 the generated atomic sequences when the 'soft-tcb' model has
1 been selected. For other models this parameter is ignored.
1 The specified value must be an integer multiple of four and in
1 the range 0-1020.
1
1 'strict'
1 This parameter prevents mixed usage of multiple atomic models,
1 even if they are compatible, and makes the compiler generate
1 atomic sequences of the specified model only.
1
1 '-mtas'
1 Generate the 'tas.b' opcode for '__atomic_test_and_set'. Notice
1 that depending on the particular hardware and software
1 configuration this can degrade overall performance due to the
1 operand cache line flushes that are implied by the 'tas.b'
1 instruction. On multi-core SH4A processors the 'tas.b' instruction
1 must be used with caution since it can result in data corruption
1 for certain cache configurations.
1
1 '-mprefergot'
1 When generating position-independent code, emit function calls
1 using the Global Offset Table instead of the Procedure Linkage
1 Table.
1
1 '-musermode'
1 '-mno-usermode'
1 Don't allow (allow) the compiler generating privileged mode code.
1 Specifying '-musermode' also implies '-mno-inline-ic_invalidate' if
1 the inlined code would not work in user mode. '-musermode' is the
1 default when the target is 'sh*-*-linux*'. If the target is SH1*
1 or SH2* '-musermode' has no effect, since there is no user mode.
1
1 '-multcost=NUMBER'
1 Set the cost to assume for a multiply insn.
1
1 '-mdiv=STRATEGY'
1 Set the division strategy to be used for integer division
1 operations. STRATEGY can be one of:
1
1 'call-div1'
1 Calls a library function that uses the single-step division
1 instruction 'div1' to perform the operation. Division by zero
1 calculates an unspecified result and does not trap. This is
1 the default except for SH4, SH2A and SHcompact.
1
1 'call-fp'
1 Calls a library function that performs the operation in double
1 precision floating point. Division by zero causes a
1 floating-point exception. This is the default for SHcompact
1 with FPU. Specifying this for targets that do not have a
1 double precision FPU defaults to 'call-div1'.
1
1 'call-table'
1 Calls a library function that uses a lookup table for small
1 divisors and the 'div1' instruction with case distinction for
1 larger divisors. Division by zero calculates an unspecified
1 result and does not trap. This is the default for SH4.
1 Specifying this for targets that do not have dynamic shift
1 instructions defaults to 'call-div1'.
1
1 When a division strategy has not been specified the default
1 strategy is selected based on the current target. For SH2A the
1 default strategy is to use the 'divs' and 'divu' instructions
1 instead of library function calls.
1
1 '-maccumulate-outgoing-args'
1 Reserve space once for outgoing arguments in the function prologue
1 rather than around each call. Generally beneficial for performance
1 and size. Also needed for unwinding to avoid changing the stack
1 frame around conditional code.
1
1 '-mdivsi3_libfunc=NAME'
1 Set the name of the library function used for 32-bit signed
1 division to NAME. This only affects the name used in the 'call'
1 division strategies, and the compiler still expects the same sets
1 of input/output/clobbered registers as if this option were not
1 present.
1
1 '-mfixed-range=REGISTER-RANGE'
1 Generate code treating the given register range as fixed registers.
1 A fixed register is one that the register allocator can not use.
1 This is useful when compiling kernel code. A register range is
1 specified as two registers separated by a dash. Multiple register
1 ranges can be specified separated by a comma.
1
1 '-mbranch-cost=NUM'
1 Assume NUM to be the cost for a branch instruction. Higher numbers
1 make the compiler try to generate more branch-free code if
1 possible. If not specified the value is selected depending on the
1 processor type that is being compiled for.
1
1 '-mzdcbranch'
1 '-mno-zdcbranch'
1 Assume (do not assume) that zero displacement conditional branch
1 instructions 'bt' and 'bf' are fast. If '-mzdcbranch' is
1 specified, the compiler prefers zero displacement branch code
1 sequences. This is enabled by default when generating code for SH4
1 and SH4A. It can be explicitly disabled by specifying
1 '-mno-zdcbranch'.
1
1 '-mcbranch-force-delay-slot'
1 Force the usage of delay slots for conditional branches, which
1 stuffs the delay slot with a 'nop' if a suitable instruction cannot
1 be found. By default this option is disabled. It can be enabled
1 to work around hardware bugs as found in the original SH7055.
1
1 '-mfused-madd'
1 '-mno-fused-madd'
1 Generate code that uses (does not use) the floating-point multiply
1 and accumulate instructions. These instructions are generated by
1 default if hardware floating point is used. The machine-dependent
1 '-mfused-madd' option is now mapped to the machine-independent
1 '-ffp-contract=fast' option, and '-mno-fused-madd' is mapped to
1 '-ffp-contract=off'.
1
1 '-mfsca'
1 '-mno-fsca'
1 Allow or disallow the compiler to emit the 'fsca' instruction for
1 sine and cosine approximations. The option '-mfsca' must be used
1 in combination with '-funsafe-math-optimizations'. It is enabled
1 by default when generating code for SH4A. Using '-mno-fsca'
1 disables sine and cosine approximations even if
1 '-funsafe-math-optimizations' is in effect.
1
1 '-mfsrra'
1 '-mno-fsrra'
1 Allow or disallow the compiler to emit the 'fsrra' instruction for
1 reciprocal square root approximations. The option '-mfsrra' must
1 be used in combination with '-funsafe-math-optimizations' and
1 '-ffinite-math-only'. It is enabled by default when generating
1 code for SH4A. Using '-mno-fsrra' disables reciprocal square root
1 approximations even if '-funsafe-math-optimizations' and
1 '-ffinite-math-only' are in effect.
1
1 '-mpretend-cmove'
1 Prefer zero-displacement conditional branches for conditional move
1 instruction patterns. This can result in faster code on the SH4
1 processor.
1
1 '-mfdpic'
1 Generate code using the FDPIC ABI.
1