gcc: DEC Alpha Options
1
1 3.18.11 DEC Alpha Options
1 -------------------------
1
1 These '-m' options are defined for the DEC Alpha implementations:
1
1 '-mno-soft-float'
1 '-msoft-float'
1 Use (do not use) the hardware floating-point instructions for
1 floating-point operations. When '-msoft-float' is specified,
1 functions in 'libgcc.a' are used to perform floating-point
1 operations. Unless they are replaced by routines that emulate the
1 floating-point operations, or compiled in such a way as to call
1 such emulations routines, these routines issue floating-point
1 operations. If you are compiling for an Alpha without
1 floating-point operations, you must ensure that the library is
1 built so as not to call them.
1
1 Note that Alpha implementations without floating-point operations
1 are required to have floating-point registers.
1
1 '-mfp-reg'
1 '-mno-fp-regs'
1 Generate code that uses (does not use) the floating-point register
1 set. '-mno-fp-regs' implies '-msoft-float'. If the floating-point
1 register set is not used, floating-point operands are passed in
1 integer registers as if they were integers and floating-point
1 results are passed in '$0' instead of '$f0'. This is a
1 non-standard calling sequence, so any function with a
1 floating-point argument or return value called by code compiled
1 with '-mno-fp-regs' must also be compiled with that option.
1
1 A typical use of this option is building a kernel that does not
1 use, and hence need not save and restore, any floating-point
1 registers.
1
1 '-mieee'
1 The Alpha architecture implements floating-point hardware optimized
1 for maximum performance. It is mostly compliant with the IEEE
1 floating-point standard. However, for full compliance, software
1 assistance is required. This option generates code fully
1 IEEE-compliant code _except_ that the INEXACT-FLAG is not
1 maintained (see below). If this option is turned on, the
1 preprocessor macro '_IEEE_FP' is defined during compilation. The
1 resulting code is less efficient but is able to correctly support
1 denormalized numbers and exceptional IEEE values such as
1 not-a-number and plus/minus infinity. Other Alpha compilers call
1 this option '-ieee_with_no_inexact'.
1
1 '-mieee-with-inexact'
1 This is like '-mieee' except the generated code also maintains the
1 IEEE INEXACT-FLAG. Turning on this option causes the generated
1 code to implement fully-compliant IEEE math. In addition to
1 '_IEEE_FP', '_IEEE_FP_EXACT' is defined as a preprocessor macro.
1 On some Alpha implementations the resulting code may execute
1 significantly slower than the code generated by default. Since
1 there is very little code that depends on the INEXACT-FLAG, you
1 should normally not specify this option. Other Alpha compilers
1 call this option '-ieee_with_inexact'.
1
1 '-mfp-trap-mode=TRAP-MODE'
1 This option controls what floating-point related traps are enabled.
1 Other Alpha compilers call this option '-fptm TRAP-MODE'. The trap
1 mode can be set to one of four values:
1
1 'n'
1 This is the default (normal) setting. The only traps that are
1 enabled are the ones that cannot be disabled in software
1 (e.g., division by zero trap).
1
1 'u'
1 In addition to the traps enabled by 'n', underflow traps are
1 enabled as well.
1
1 'su'
1 Like 'u', but the instructions are marked to be safe for
1 software completion (see Alpha architecture manual for
1 details).
1
1 'sui'
1 Like 'su', but inexact traps are enabled as well.
1
1 '-mfp-rounding-mode=ROUNDING-MODE'
1 Selects the IEEE rounding mode. Other Alpha compilers call this
1 option '-fprm ROUNDING-MODE'. The ROUNDING-MODE can be one of:
1
1 'n'
1 Normal IEEE rounding mode. Floating-point numbers are rounded
1 towards the nearest machine number or towards the even machine
1 number in case of a tie.
1
1 'm'
1 Round towards minus infinity.
1
1 'c'
1 Chopped rounding mode. Floating-point numbers are rounded
1 towards zero.
1
1 'd'
1 Dynamic rounding mode. A field in the floating-point control
1 register (FPCR, see Alpha architecture reference manual)
1 controls the rounding mode in effect. The C library
1 initializes this register for rounding towards plus infinity.
1 Thus, unless your program modifies the FPCR, 'd' corresponds
1 to round towards plus infinity.
1
1 '-mtrap-precision=TRAP-PRECISION'
1 In the Alpha architecture, floating-point traps are imprecise.
1 This means without software assistance it is impossible to recover
1 from a floating trap and program execution normally needs to be
1 terminated. GCC can generate code that can assist operating system
1 trap handlers in determining the exact location that caused a
1 floating-point trap. Depending on the requirements of an
1 application, different levels of precisions can be selected:
1
1 'p'
1 Program precision. This option is the default and means a
1 trap handler can only identify which program caused a
1 floating-point exception.
1
1 'f'
1 Function precision. The trap handler can determine the
1 function that caused a floating-point exception.
1
1 'i'
1 Instruction precision. The trap handler can determine the
1 exact instruction that caused a floating-point exception.
1
1 Other Alpha compilers provide the equivalent options called
1 '-scope_safe' and '-resumption_safe'.
1
1 '-mieee-conformant'
1 This option marks the generated code as IEEE conformant. You must
1 not use this option unless you also specify '-mtrap-precision=i'
1 and either '-mfp-trap-mode=su' or '-mfp-trap-mode=sui'. Its only
1 effect is to emit the line '.eflag 48' in the function prologue of
1 the generated assembly file.
1
1 '-mbuild-constants'
1 Normally GCC examines a 32- or 64-bit integer constant to see if it
1 can construct it from smaller constants in two or three
1 instructions. If it cannot, it outputs the constant as a literal
1 and generates code to load it from the data segment at run time.
1
1 Use this option to require GCC to construct _all_ integer constants
1 using code, even if it takes more instructions (the maximum is
1 six).
1
1 You typically use this option to build a shared library dynamic
1 loader. Itself a shared library, it must relocate itself in memory
1 before it can find the variables and constants in its own data
1 segment.
1
1 '-mbwx'
1 '-mno-bwx'
1 '-mcix'
1 '-mno-cix'
1 '-mfix'
1 '-mno-fix'
1 '-mmax'
1 '-mno-max'
1 Indicate whether GCC should generate code to use the optional BWX,
1 CIX, FIX and MAX instruction sets. The default is to use the
1 instruction sets supported by the CPU type specified via '-mcpu='
1 option or that of the CPU on which GCC was built if none is
1 specified.
1
1 '-mfloat-vax'
1 '-mfloat-ieee'
1 Generate code that uses (does not use) VAX F and G floating-point
1 arithmetic instead of IEEE single and double precision.
1
1 '-mexplicit-relocs'
1 '-mno-explicit-relocs'
1 Older Alpha assemblers provided no way to generate symbol
1 relocations except via assembler macros. Use of these macros does
1 not allow optimal instruction scheduling. GNU binutils as of
1 version 2.12 supports a new syntax that allows the compiler to
1 explicitly mark which relocations should apply to which
1 instructions. This option is mostly useful for debugging, as GCC
1 detects the capabilities of the assembler when it is built and sets
1 the default accordingly.
1
1 '-msmall-data'
1 '-mlarge-data'
1 When '-mexplicit-relocs' is in effect, static data is accessed via
1 "gp-relative" relocations. When '-msmall-data' is used, objects 8
1 bytes long or smaller are placed in a "small data area" (the
1 '.sdata' and '.sbss' sections) and are accessed via 16-bit
1 relocations off of the '$gp' register. This limits the size of the
1 small data area to 64KB, but allows the variables to be directly
1 accessed via a single instruction.
1
1 The default is '-mlarge-data'. With this option the data area is
1 limited to just below 2GB. Programs that require more than 2GB of
1 data must use 'malloc' or 'mmap' to allocate the data in the heap
1 instead of in the program's data segment.
1
1 When generating code for shared libraries, '-fpic' implies
1 '-msmall-data' and '-fPIC' implies '-mlarge-data'.
1
1 '-msmall-text'
1 '-mlarge-text'
1 When '-msmall-text' is used, the compiler assumes that the code of
1 the entire program (or shared library) fits in 4MB, and is thus
1 reachable with a branch instruction. When '-msmall-data' is used,
1 the compiler can assume that all local symbols share the same '$gp'
1 value, and thus reduce the number of instructions required for a
1 function call from 4 to 1.
1
1 The default is '-mlarge-text'.
1
1 '-mcpu=CPU_TYPE'
1 Set the instruction set and instruction scheduling parameters for
1 machine type CPU_TYPE. You can specify either the 'EV' style name
1 or the corresponding chip number. GCC supports scheduling
1 parameters for the EV4, EV5 and EV6 family of processors and
1 chooses the default values for the instruction set from the
1 processor you specify. If you do not specify a processor type, GCC
1 defaults to the processor on which the compiler was built.
1
1 Supported values for CPU_TYPE are
1
1 'ev4'
1 'ev45'
1 '21064'
1 Schedules as an EV4 and has no instruction set extensions.
1
1 'ev5'
1 '21164'
1 Schedules as an EV5 and has no instruction set extensions.
1
1 'ev56'
1 '21164a'
1 Schedules as an EV5 and supports the BWX extension.
1
1 'pca56'
1 '21164pc'
1 '21164PC'
1 Schedules as an EV5 and supports the BWX and MAX extensions.
1
1 'ev6'
1 '21264'
1 Schedules as an EV6 and supports the BWX, FIX, and MAX
1 extensions.
1
1 'ev67'
1 '21264a'
1 Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX
1 extensions.
1
1 Native toolchains also support the value 'native', which selects
1 the best architecture option for the host processor.
1 '-mcpu=native' has no effect if GCC does not recognize the
1 processor.
1
1 '-mtune=CPU_TYPE'
1 Set only the instruction scheduling parameters for machine type
1 CPU_TYPE. The instruction set is not changed.
1
1 Native toolchains also support the value 'native', which selects
1 the best architecture option for the host processor.
1 '-mtune=native' has no effect if GCC does not recognize the
1 processor.
1
1 '-mmemory-latency=TIME'
1 Sets the latency the scheduler should assume for typical memory
1 references as seen by the application. This number is highly
1 dependent on the memory access patterns used by the application and
1 the size of the external cache on the machine.
1
1 Valid options for TIME are
1
1 'NUMBER'
1 A decimal number representing clock cycles.
1
1 'L1'
1 'L2'
1 'L3'
1 'main'
1 The compiler contains estimates of the number of clock cycles
1 for "typical" EV4 & EV5 hardware for the Level 1, 2 & 3 caches
1 (also called Dcache, Scache, and Bcache), as well as to main
1 memory. Note that L3 is only valid for EV5.
1