as: s390 Mnemonics

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1 9.40.3.2 Instruction Mnemonics
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1 All instructions documented in the Principles of Operation are supported
1 with the mnemonic and order of operands as described.  The instruction
1 mnemonic identifies the instruction format (⇒s390 Formats) and
1 the specific operation code for the instruction.  For example, the 'lr'
1 mnemonic denotes the instruction format 'RR' with the operation code
1 '0x18'.
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1    The definition of the various mnemonics follows a scheme, where the
1 first character usually hint at the type of the instruction:
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1      a          add instruction, for example 'al' for add logical 32-bit
1      b          branch instruction, for example 'bc' for branch on condition
1      c          compare or convert instruction, for example 'cr' for compare
1                 register 32-bit
1      d          divide instruction, for example 'dlr' devide logical register
1                 64-bit to 32-bit
1      i          insert instruction, for example 'ic' insert character
1      l          load instruction, for example 'ltr' load and test register
1      mv         move instruction, for example 'mvc' move character
1      m          multiply instruction, for example 'mh' multiply halfword
1      n          and instruction, for example 'ni' and immediate
1      o          or instruction, for example 'oc' or character
1      sla, sll   shift left single instruction
1      sra, srl   shift right single instruction
1      st         store instruction, for example 'stm' store multiple
1      s          subtract instruction, for example 'slr' subtract
1                 logical 32-bit
1      t          test or translate instruction, of example 'tm' test under mask
1      x          exclusive or instruction, for example 'xc' exclusive or
1                 character
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1    Certain characters at the end of the mnemonic may describe a property
1 of the instruction:
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1      c   the instruction uses a 8-bit character operand
1      f   the instruction extends a 32-bit operand to 64 bit
1      g   the operands are treated as 64-bit values
1      h   the operand uses a 16-bit halfword operand
1      i   the instruction uses an immediate operand
1      l   the instruction uses unsigned, logical operands
1      m   the instruction uses a mask or operates on multiple values
1      r   if r is the last character, the instruction operates on registers
1      y   the instruction uses 20-bit displacements
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1    There are many exceptions to the scheme outlined in the above lists,
1 in particular for the privileged instructions.  For non-privileged
1 instruction it works quite well, for example the instruction 'clgfr' c:
1 compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to
1 64-bit extension, r: register operands.  The instruction compares an
1 64-bit value in a register with the zero extended 32-bit value from a
1 second register.  For a complete list of all mnemonics see appendix B in
1 the Principles of Operation.
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