as: i386-Options
1
1 9.15.1 Options
1 --------------
1
1 The i386 version of 'as' has a few machine dependent options:
1
1 '--32 | --x32 | --64'
1 Select the word size, either 32 bits or 64 bits. '--32' implies
1 Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64
1 architecture with 32-bit or 64-bit word-size respectively.
1
1 These options are only available with the ELF object file format,
1 and require that the necessary BFD support has been included (on a
1 32-bit platform you have to add -enable-64-bit-bfd to configure
1 enable 64-bit usage and use x86-64 as target platform).
1
1 '-n'
1 By default, x86 GAS replaces multiple nop instructions used for
1 alignment within code sections with multi-byte nop instructions
1 such as leal 0(%esi,1),%esi. This switch disables the optimization
1 if a single byte nop (0x90) is explicitly specified as the fill
1 byte for alignment.
1
1 '--divide'
1 On SVR4-derived platforms, the character '/' is treated as a
1 comment character, which means that it cannot be used in
1 expressions. The '--divide' option turns '/' into a normal
1 character. This does not disable '/' at the beginning of a line
1 starting a comment, or affect using '#' for starting a comment.
1
1 '-march=CPU[+EXTENSION...]'
1 This option specifies the target processor. The assembler will
1 issue an error message if an attempt is made to assemble an
1 instruction which will not execute on the target processor. The
1 following processor names are recognized: 'i8086', 'i186', 'i286',
1 'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro',
1 'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona',
1 'core', 'core2', 'corei7', 'l1om', 'k1om', 'iamcu', 'k6', 'k6_2',
1 'athlon', 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2',
1 'bdver3', 'bdver4', 'znver1', 'znver2', 'btver1', 'btver2',
1 'generic32' and 'generic64'.
1
1 In addition to the basic instruction set, the assembler can be told
1 to accept various extension mnemonics. For example,
1 '-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
1 following extensions are currently supported: '8087', '287', '387',
1 '687', 'no87', 'no287', 'no387', 'no687', 'mmx', 'nommx', 'sse',
1 'sse2', 'sse3', 'ssse3', 'sse4.1', 'sse4.2', 'sse4', 'nosse',
1 'nosse2', 'nosse3', 'nossse3', 'nosse4.1', 'nosse4.2', 'nosse4',
1 'avx', 'avx2', 'noavx', 'noavx2', 'adx', 'rdseed', 'prfchw',
1 'smap', 'mpx', 'sha', 'rdpid', 'ptwrite', 'cet', 'gfni', 'vaes',
1 'vpclmulqdq', 'prefetchwt1', 'clflushopt', 'se1', 'clwb',
1 'movdiri', 'movdir64b', 'avx512f', 'avx512cd', 'avx512er',
1 'avx512pf', 'avx512vl', 'avx512bw', 'avx512dq', 'avx512ifma',
1 'avx512vbmi', 'avx512_4fmaps', 'avx512_4vnniw', 'avx512_vpopcntdq',
1 'avx512_vbmi2', 'avx512_vnni', 'avx512_bitalg', 'noavx512f',
1 'noavx512cd', 'noavx512er', 'noavx512pf', 'noavx512vl',
1 'noavx512bw', 'noavx512dq', 'noavx512ifma', 'noavx512vbmi',
1 'noavx512_4fmaps', 'noavx512_4vnniw', 'noavx512_vpopcntdq',
1 'noavx512_vbmi2', 'noavx512_vnni', 'noavx512_bitalg', 'vmx',
1 'vmfunc', 'smx', 'xsave', 'xsaveopt', 'xsavec', 'xsaves', 'aes',
1 'pclmul', 'fsgsbase', 'rdrnd', 'f16c', 'bmi2', 'fma', 'movbe',
1 'ept', 'lzcnt', 'hle', 'rtm', 'invpcid', 'clflush', 'mwaitx',
1 'clzero', 'wbnoinvd', 'pconfig', 'waitpkg', 'cldemote', 'lwp',
1 'fma4', 'xop', 'cx16', 'syscall', 'rdtscp', '3dnow', '3dnowa',
1 'sse4a', 'sse5', 'svme', 'abm' and 'padlock'. Note that rather
1 than extending a basic instruction set, the extension mnemonics
1 starting with 'no' revoke the respective functionality.
1
1 When the '.arch' directive is used with '-march', the '.arch'
1 directive will take precedent.
1
1 '-mtune=CPU'
1 This option specifies a processor to optimize for. When used in
1 conjunction with the '-march' option, only instructions of the
1 processor specified by the '-march' option will be generated.
1
1 Valid CPU values are identical to the processor list of
1 '-march=CPU'.
1
1 '-msse2avx'
1 This option specifies that the assembler should encode SSE
1 instructions with VEX prefix.
1
1 '-msse-check=NONE'
1 '-msse-check=WARNING'
1 '-msse-check=ERROR'
1 These options control if the assembler should check SSE
1 instructions. '-msse-check=NONE' will make the assembler not to
1 check SSE instructions, which is the default.
1 '-msse-check=WARNING' will make the assembler issue a warning for
1 any SSE instruction. '-msse-check=ERROR' will make the assembler
1 issue an error for any SSE instruction.
1
1 '-mavxscalar=128'
1 '-mavxscalar=256'
1 These options control how the assembler should encode scalar AVX
1 instructions. '-mavxscalar=128' will encode scalar AVX
1 instructions with 128bit vector length, which is the default.
1 '-mavxscalar=256' will encode scalar AVX instructions with 256bit
1 vector length.
1
1 '-mevexlig=128'
1 '-mevexlig=256'
1 '-mevexlig=512'
1 These options control how the assembler should encode
1 length-ignored (LIG) EVEX instructions. '-mevexlig=128' will
1 encode LIG EVEX instructions with 128bit vector length, which is
1 the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG
1 EVEX instructions with 256bit and 512bit vector length,
1 respectively.
1
1 '-mevexwig=0'
1 '-mevexwig=1'
1 These options control how the assembler should encode w-ignored
1 (WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX
1 instructions with evex.w = 0, which is the default. '-mevexwig=1'
1 will encode WIG EVEX instructions with evex.w = 1.
1
1 '-mmnemonic=ATT'
1 '-mmnemonic=INTEL'
1 This option specifies instruction mnemonic for matching
1 instructions. The '.att_mnemonic' and '.intel_mnemonic' directives
1 will take precedent.
1
1 '-msyntax=ATT'
1 '-msyntax=INTEL'
1 This option specifies instruction syntax when processing
1 instructions. The '.att_syntax' and '.intel_syntax' directives
1 will take precedent.
1
1 '-mnaked-reg'
1 This option specifies that registers don't require a '%' prefix.
1 The '.att_syntax' and '.intel_syntax' directives will take
1 precedent.
1
1 '-madd-bnd-prefix'
1 This option forces the assembler to add BND prefix to all branches,
1 even if such prefix was not explicitly specified in the source
1 code.
1
1 '-mno-shared'
1 On ELF target, the assembler normally optimizes out non-PLT
1 relocations against defined non-weak global branch targets with
1 default visibility. The '-mshared' option tells the assembler to
1 generate code which may go into a shared library where all non-weak
1 global branch targets with default visibility can be preempted.
1 The resulting code is slightly bigger. This option only affects
1 the handling of branch instructions.
1
1 '-mbig-obj'
1 On x86-64 PE/COFF target this option forces the use of big object
1 file format, which allows more than 32768 sections.
1
1 '-momit-lock-prefix=NO'
1 '-momit-lock-prefix=YES'
1 These options control how the assembler should encode lock prefix.
1 This option is intended as a workaround for processors, that fail
1 on lock prefix. This option can only be safely used with
1 single-core, single-thread computers '-momit-lock-prefix=YES' will
1 omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock
1 prefix as usual, which is the default.
1
1 '-mfence-as-lock-add=NO'
1 '-mfence-as-lock-add=YES'
1 These options control how the assembler should encode lfence,
1 mfence and sfence. '-mfence-as-lock-add=YES' will encode lfence,
1 mfence and sfence as 'lock addl $0x0, (%rsp)' in 64-bit mode and
1 'lock addl $0x0, (%esp)' in 32-bit mode. '-mfence-as-lock-add=NO'
1 will encode lfence, mfence and sfence as usual, which is the
1 default.
1
1 '-mrelax-relocations=NO'
1 '-mrelax-relocations=YES'
1 These options control whether the assembler should generate relax
1 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1 '-mrelax-relocations=YES' will generate relax relocations.
1 '-mrelax-relocations=NO' will not generate relax relocations. The
1 default can be controlled by a configure option
1 '--enable-x86-relax-relocations'.
1
1 '-mevexrcig=RNE'
1 '-mevexrcig=RD'
1 '-mevexrcig=RU'
1 '-mevexrcig=RZ'
1 These options control how the assembler should encode SAE-only EVEX
1 instructions. '-mevexrcig=RNE' will encode RC bits of EVEX
1 instruction with 00, which is the default. '-mevexrcig=RD',
1 '-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX
1 instructions with 01, 10 and 11 RC bits, respectively.
1
1 '-mamd64'
1 '-mintel64'
1 This option specifies that the assembler should accept only AMD64
1 or Intel64 ISA in 64-bit mode. The default is to accept both.
1
1 '-O0 | -O | -O1 | -O2 | -Os'
1 Optimize instruction encoding with smaller instruction size. '-O'
1 and '-O1' encode 64-bit register load instructions with 64-bit
1 immediate as 32-bit register load instructions with 31-bit or
1 32-bits immediates and encode 64-bit register clearing instructions
1 with 32-bit register clearing instructions. '-O2' includes '-O1'
1 optimization plus encodes 256-bit and 512-bit vector register
1 clearing instructions with 128-bit vector register clearing
1 instructions. '-Os' includes '-O2' optimization plus encodes
1 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit
1 register test with immediate. '-O0' turns off this optimization.
1