as: i386-Arch

1 
1 9.15.15 Specifying CPU Architecture
1 -----------------------------------
1 
1 'as' may be told to assemble for a particular CPU (sub-)architecture
1 with the '.arch CPU_TYPE' directive.  This directive enables a warning
1 when gas detects an instruction that is not supported on the CPU
1 specified.  The choices for CPU_TYPE are:
1 
1 'i8086'        'i186'         'i286'         'i386'
1 'i486'         'i586'         'i686'         'pentium'
1 'pentiumpro'   'pentiumii'    'pentiumiii'   'pentium4'
1 'prescott'     'nocona'       'core'         'core2'
1 'corei7'       'l1om'         'k1om'
1                               'iamcu'
1 'k6'           'k6_2'         'athlon'       'k8'
1 'amdfam10'     'bdver1'       'bdver2'       'bdver3'
1 'bdver4'       'znver1'       'znver2'       'btver1'
1 'btver2'       'generic64'
1 'generic32'
1 '.mmx'         '.sse'         '.sse2'        '.sse3'
1 '.ssse3'       '.sse4.1'      '.sse4.2'      '.sse4'
1 '.avx'         '.vmx'         '.smx'         '.ept'
1 '.clflush'     '.movbe'       '.xsave'       '.xsaveopt'
1 '.aes'         '.pclmul'      '.fma'         '.fsgsbase'
1 '.rdrnd'       '.f16c'        '.avx2'        '.bmi2'
1 '.lzcnt'       '.invpcid'     '.vmfunc'      '.hle'
1 '.rtm'         '.adx'         '.rdseed'      '.prfchw'
1 '.smap'        '.mpx'         '.sha'         '.prefetchwt1'
1 '.clflushopt'  '.xsavec'      '.xsaves'      '.se1'
1 '.avx512f'     '.avx512cd'    '.avx512er'    '.avx512pf'
1 '.avx512vl'    '.avx512bw'    '.avx512dq'    '.avx512ifma'
1 '.avx512vbmi'  '.avx512_4fmaps''.avx512_4vnniw'
1 '.avx512_vpopcntdq''.avx512_vbmi2''.avx512_vnni'
1 '.avx512_bitalg'
1 '.clwb'        '.rdpid'       '.ptwrite'
1 '.ibt'
1 '.wbnoinvd'    '.pconfig'     '.waitpkg'     '.cldemote'
1 '.shstk'       '.gfni'        '.vaes'        '.vpclmulqdq'
1 '.movdiri'     '.movdir64b'
1 '.3dnow'       '.3dnowa'      '.sse4a'       '.sse5'
1 '.syscall'     '.rdtscp'      '.svme'        '.abm'
1 '.lwp'         '.fma4'        '.xop'         '.cx16'
1 '.padlock'     '.clzero'      '.mwaitx'
1 
1    Apart from the warning, there are only two other effects on 'as'
1 operation; Firstly, if you specify a CPU other than 'i486', then shift
1 by one instructions such as 'sarl $1, %eax' will automatically use a two
1 byte opcode sequence.  The larger three byte opcode sequence is used on
1 the 486 (and when no architecture is specified) because it executes
1 faster on the 486.  Note that you can explicitly request the two byte
1 opcode by writing 'sarl %eax'.  Secondly, if you specify 'i8086',
1 'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset
1 conditional jumps will be promoted when necessary to a two instruction
1 sequence consisting of a conditional jump of the opposite sense around
1 an unconditional jump to the target.
1 
1    Following the CPU architecture (but not a sub-architecture, which are
1 those starting with a dot), you may specify 'jumps' or 'nojumps' to
1 control automatic promotion of conditional jumps.  'jumps' is the
1 default, and enables jump promotion; All external jumps will be of the
1 long variety, and file-local jumps will be promoted as necessary.
1 (⇒i386-Jumps) 'nojumps' leaves external conditional jumps as byte
1 offset jumps, and warns about file-local conditional jumps that 'as'
1 promotes.  Unconditional jumps are treated as for 'jumps'.
1 
1    For example
1 
1       .arch i8086,nojumps
1