as: Sparc-Size-Translations

1 
1 9.44.3.5 Size Translations
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1 
1 Often it is desirable to write code in an operand size agnostic manner.
1 'as' provides support for this via operand size opcode translations.
1 Translations are supported for loads, stores, shifts, compare-and-swap
1 atomics, and the 'clr' synthetic instruction.
1 
1    If generating 32-bit code, 'as' will generate the 32-bit opcode.
1 Whereas if 64-bit code is being generated, the 64-bit opcode will be
1 emitted.  For example 'ldn' will be transformed into 'ld' for 32-bit
1 code and 'ldx' for 64-bit code.
1 
1    Here is an example meant to demonstrate all the supported opcode
1 translations:
1 
1      ldn   [%o0], %o1
1      ldna  [%o0] %asi, %o2
1      stn   %o1, [%o0]
1      stna  %o2, [%o0] %asi
1      slln  %o3, 3, %o3
1      srln  %o4, 8, %o4
1      sran  %o5, 12, %o5
1      casn  [%o0], %o1, %o2
1      casna [%o0] %asi, %o1, %o2
1      clrn  %g1
1 
1    In 32-bit mode 'as' will emit:
1 
1      ld   [%o0], %o1
1      lda  [%o0] %asi, %o2
1      st   %o1, [%o0]
1      sta  %o2, [%o0] %asi
1      sll  %o3, 3, %o3
1      srl  %o4, 8, %o4
1      sra  %o5, 12, %o5
1      cas  [%o0], %o1, %o2
1      casa [%o0] %asi, %o1, %o2
1      clr  %g1
1 
1    And in 64-bit mode 'as' will emit:
1 
1      ldx   [%o0], %o1
1      ldxa  [%o0] %asi, %o2
1      stx   %o1, [%o0]
1      stxa  %o2, [%o0] %asi
1      sllx  %o3, 3, %o3
1      srlx  %o4, 8, %o4
1      srax  %o5, 12, %o5
1      casx  [%o0], %o1, %o2
1      casxa [%o0] %asi, %o1, %o2
1      clrx  %g1
1 
1    Finally, the '.nword' translating directive is supported as well.  It
1 is documented in the section on Sparc machine directives.
1