as: Sparc-Constants

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1 9.44.3.3 Constants
1 ..................
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1 Several Sparc instructions take an immediate operand field for which
1 mnemonic names exist.  Two such examples are 'membar' and 'prefetch'.
1 Another example are the set of V9 memory access instruction that allow
1 specification of an address space identifier.
1 
1    The 'membar' instruction specifies a memory barrier that is the
1 defined by the operand which is a bitmask.  The supported mask mnemonics
1 are:
1 
1    * '#Sync' requests that all operations (including nonmemory reference
1      operations) appearing prior to the 'membar' must have been
1      performed and the effects of any exceptions become visible before
1      any instructions after the 'membar' may be initiated.  This
1      corresponds to 'membar' cmask field bit 2.
1 
1    * '#MemIssue' requests that all memory reference operations appearing
1      prior to the 'membar' must have been performed before any memory
1      operation after the 'membar' may be initiated.  This corresponds to
1      'membar' cmask field bit 1.
1 
1    * '#Lookaside' requests that a store appearing prior to the 'membar'
1      must complete before any load following the 'membar' referencing
1      the same address can be initiated.  This corresponds to 'membar'
1      cmask field bit 0.
1 
1    * '#StoreStore' defines that the effects of all stores appearing
1      prior to the 'membar' instruction must be visible to all processors
1      before the effect of any stores following the 'membar'.  Equivalent
1      to the deprecated 'stbar' instruction.  This corresponds to
1      'membar' mmask field bit 3.
1 
1    * '#LoadStore' defines all loads appearing prior to the 'membar'
1      instruction must have been performed before the effect of any
1      stores following the 'membar' is visible to any other processor.
1      This corresponds to 'membar' mmask field bit 2.
1 
1    * '#StoreLoad' defines that the effects of all stores appearing prior
1      to the 'membar' instruction must be visible to all processors
1      before loads following the 'membar' may be performed.  This
1      corresponds to 'membar' mmask field bit 1.
1 
1    * '#LoadLoad' defines that all loads appearing prior to the 'membar'
1      instruction must have been performed before any loads following the
1      'membar' may be performed.  This corresponds to 'membar' mmask
1      field bit 0.
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1    These values can be ored together, for example:
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1      membar #Sync
1      membar #StoreLoad | #LoadLoad
1      membar #StoreLoad | #StoreStore
1 
1    The 'prefetch' and 'prefetcha' instructions take a prefetch function
1 code.  The following prefetch function code constant mnemonics are
1 available:
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1    * '#n_reads' requests a prefetch for several reads, and corresponds
1      to a prefetch function code of 0.
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1      '#one_read' requests a prefetch for one read, and corresponds to a
1      prefetch function code of 1.
1 
1      '#n_writes' requests a prefetch for several writes (and possibly
1      reads), and corresponds to a prefetch function code of 2.
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1      '#one_write' requests a prefetch for one write, and corresponds to
1      a prefetch function code of 3.
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1      '#page' requests a prefetch page, and corresponds to a prefetch
1      function code of 4.
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1      '#invalidate' requests a prefetch invalidate, and corresponds to a
1      prefetch function code of 16.
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1      '#unified' requests a prefetch to the nearest unified cache, and
1      corresponds to a prefetch function code of 17.
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1      '#n_reads_strong' requests a strong prefetch for several reads, and
1      corresponds to a prefetch function code of 20.
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1      '#one_read_strong' requests a strong prefetch for one read, and
1      corresponds to a prefetch function code of 21.
1 
1      '#n_writes_strong' requests a strong prefetch for several writes,
1      and corresponds to a prefetch function code of 22.
1 
1      '#one_write_strong' requests a strong prefetch for one write, and
1      corresponds to a prefetch function code of 23.
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1      Onle one prefetch code may be specified.  Here are some examples:
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1           prefetch  [%l0 + %l2], #one_read
1           prefetch  [%g2 + 8], #n_writes
1           prefetcha [%g1] 0x8, #unified
1           prefetcha [%o0 + 0x10] %asi, #n_reads
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1      The actual behavior of a given prefetch function code is processor
1      specific.  If a processor does not implement a given prefetch
1      function code, it will treat the prefetch instruction as a nop.
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1      For instructions that accept an immediate address space identifier,
1      'as' provides many mnemonics corresponding to V9 defined as well as
1      UltraSPARC and Niagara extended values.  For example, '#ASI_P' and
1      '#ASI_BLK_INIT_QUAD_LDD_AIUS'.  See the V9 and processor specific
1      manuals for details.
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