as: SH Opcodes
1
1 9.42.5 Opcodes
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1
1 For detailed information on the SH machine instruction set, see
1 'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core
1 Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH).
1
1 'as' implements all the standard SH opcodes. No additional
1 pseudo-instructions are needed on this family. Note, however, that
1 because 'as' supports a simpler form of PC-relative addressing, you may
1 simply write (for example)
1
1 mov.l bar,r0
1
1 where other assemblers might require an explicit displacement to 'bar'
1 from the program counter:
1
1 mov.l @(DISP, PC)
1
1 Here is a summary of SH opcodes:
1
1 Legend:
1 Rn a numbered register
1 Rm another numbered register
1 #imm immediate data
1 disp displacement
1 disp8 8-bit displacement
1 disp12 12-bit displacement
1
1 add #imm,Rn lds.l @Rn+,PR
1 add Rm,Rn mac.w @Rm+,@Rn+
1 addc Rm,Rn mov #imm,Rn
1 addv Rm,Rn mov Rm,Rn
1 and #imm,R0 mov.b Rm,@(R0,Rn)
1 and Rm,Rn mov.b Rm,@-Rn
1 and.b #imm,@(R0,GBR) mov.b Rm,@Rn
1 bf disp8 mov.b @(disp,Rm),R0
1 bra disp12 mov.b @(disp,GBR),R0
1 bsr disp12 mov.b @(R0,Rm),Rn
1 bt disp8 mov.b @Rm+,Rn
1 clrmac mov.b @Rm,Rn
1 clrt mov.b R0,@(disp,Rm)
1 cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
1 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
1 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
1 cmp/gt Rm,Rn mov.l Rm,@-Rn
1 cmp/hi Rm,Rn mov.l Rm,@Rn
1 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
1 cmp/pl Rn mov.l @(disp,GBR),R0
1 cmp/pz Rn mov.l @(disp,PC),Rn
1 cmp/str Rm,Rn mov.l @(R0,Rm),Rn
1 div0s Rm,Rn mov.l @Rm+,Rn
1 div0u mov.l @Rm,Rn
1 div1 Rm,Rn mov.l R0,@(disp,GBR)
1 exts.b Rm,Rn mov.w Rm,@(R0,Rn)
1 exts.w Rm,Rn mov.w Rm,@-Rn
1 extu.b Rm,Rn mov.w Rm,@Rn
1 extu.w Rm,Rn mov.w @(disp,Rm),R0
1 jmp @Rn mov.w @(disp,GBR),R0
1 jsr @Rn mov.w @(disp,PC),Rn
1 ldc Rn,GBR mov.w @(R0,Rm),Rn
1 ldc Rn,SR mov.w @Rm+,Rn
1 ldc Rn,VBR mov.w @Rm,Rn
1 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
1 ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
1 ldc.l @Rn+,VBR mova @(disp,PC),R0
1 lds Rn,MACH movt Rn
1 lds Rn,MACL muls Rm,Rn
1 lds Rn,PR mulu Rm,Rn
1 lds.l @Rn+,MACH neg Rm,Rn
1 lds.l @Rn+,MACL negc Rm,Rn
1 nop stc VBR,Rn
1 not Rm,Rn stc.l GBR,@-Rn
1 or #imm,R0 stc.l SR,@-Rn
1 or Rm,Rn stc.l VBR,@-Rn
1 or.b #imm,@(R0,GBR) sts MACH,Rn
1 rotcl Rn sts MACL,Rn
1 rotcr Rn sts PR,Rn
1 rotl Rn sts.l MACH,@-Rn
1 rotr Rn sts.l MACL,@-Rn
1 rte sts.l PR,@-Rn
1 rts sub Rm,Rn
1 sett subc Rm,Rn
1 shal Rn subv Rm,Rn
1 shar Rn swap.b Rm,Rn
1 shll Rn swap.w Rm,Rn
1 shll16 Rn tas.b @Rn
1 shll2 Rn trapa #imm
1 shll8 Rn tst #imm,R0
1 shlr Rn tst Rm,Rn
1 shlr16 Rn tst.b #imm,@(R0,GBR)
1 shlr2 Rn xor #imm,R0
1 shlr8 Rn xor Rm,Rn
1 sleep xor.b #imm,@(R0,GBR)
1 stc GBR,Rn xtrct Rm,Rn
1 stc SR,Rn
1