as: SH Floating Point

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1 9.42.3 Floating Point
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1 SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
1 SH groups can use '.float' directive to generate IEEE floating-point
1 numbers.
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1    SH2E and SH3E support single-precision floating point calculations as
1 well as entirely PCAPI compatible emulation of double-precision floating
1 point calculations.  SH2E and SH3E instructions are a subset of the
1 floating point calculations conforming to the IEEE754 standard.
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1    In addition to single-precision and double-precision floating-point
1 operation capability, the on-chip FPU of SH4 has a 128-bit graphic
1 engine that enables 32-bit floating-point data to be processed 128 bits
1 at a time.  It also supports 4 * 4 array operations and inner product
1 operations.  Also, a superscalar architecture is employed that enables
1 simultaneous execution of two instructions (including FPU instructions),
1 providing performance of up to twice that of conventional architectures
1 at the same frequency.
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