as: PowerPC-Opts

1 
1 9.35.1 Options
1 --------------
1 
1 The PowerPC chip family includes several successive levels, using the
1 same core instruction set, but including a few additional instructions
1 at each level.  There are exceptions to this however.  For details on
1 what instructions each variant supports, please see the chip's
1 architecture reference manual.
1 
1    The following table lists all available PowerPC options.
1 
1 '-a32'
1      Generate ELF32 or XCOFF32.
1 
1 '-a64'
1      Generate ELF64 or XCOFF64.
1 
1 '-K PIC'
1      Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1 
1 '-mpwrx | -mpwr2'
1      Generate code for POWER/2 (RIOS2).
1 
1 '-mpwr'
1      Generate code for POWER (RIOS1)
1 
1 '-m601'
1      Generate code for PowerPC 601.
1 
1 '-mppc, -mppc32, -m603, -m604'
1      Generate code for PowerPC 603/604.
1 
1 '-m403, -m405'
1      Generate code for PowerPC 403/405.
1 
1 '-m440'
1      Generate code for PowerPC 440.  BookE and some 405 instructions.
1 
1 '-m464'
1      Generate code for PowerPC 464.
1 
1 '-m476'
1      Generate code for PowerPC 476.
1 
1 '-m7400, -m7410, -m7450, -m7455'
1      Generate code for PowerPC 7400/7410/7450/7455.
1 
1 '-m750cl'
1      Generate code for PowerPC 750CL.
1 
1 '-m821, -m850, -m860'
1      Generate code for PowerPC 821/850/860.
1 
1 '-mppc64, -m620'
1      Generate code for PowerPC 620/625/630.
1 
1 '-me500, -me500x2'
1      Generate code for Motorola e500 core complex.
1 
1 '-me500mc'
1      Generate code for Freescale e500mc core complex.
1 
1 '-me500mc64'
1      Generate code for Freescale e500mc64 core complex.
1 
1 '-me5500'
1      Generate code for Freescale e5500 core complex.
1 
1 '-me6500'
1      Generate code for Freescale e6500 core complex.
1 
1 '-mspe'
1      Generate code for Motorola SPE instructions.
1 
1 '-mspe2'
1      Generate code for Freescale SPE2 instructions.
1 
1 '-mtitan'
1      Generate code for AppliedMicro Titan core complex.
1 
1 '-mppc64bridge'
1      Generate code for PowerPC 64, including bridge insns.
1 
1 '-mbooke'
1      Generate code for 32-bit BookE.
1 
1 '-ma2'
1      Generate code for A2 architecture.
1 
1 '-me300'
1      Generate code for PowerPC e300 family.
1 
1 '-maltivec'
1      Generate code for processors with AltiVec instructions.
1 
1 '-mvle'
1      Generate code for Freescale PowerPC VLE instructions.
1 
1 '-mvsx'
1      Generate code for processors with Vector-Scalar (VSX) instructions.
1 
1 '-mhtm'
1      Generate code for processors with Hardware Transactional Memory
1      instructions.
1 
1 '-mpower4, -mpwr4'
1      Generate code for Power4 architecture.
1 
1 '-mpower5, -mpwr5, -mpwr5x'
1      Generate code for Power5 architecture.
1 
1 '-mpower6, -mpwr6'
1      Generate code for Power6 architecture.
1 
1 '-mpower7, -mpwr7'
1      Generate code for Power7 architecture.
1 
1 '-mpower8, -mpwr8'
1      Generate code for Power8 architecture.
1 
1 '-mpower9, -mpwr9'
1      Generate code for Power9 architecture.
1 
1 '-mcell'
1 '-mcell'
1      Generate code for Cell Broadband Engine architecture.
1 
1 '-mcom'
1      Generate code Power/PowerPC common instructions.
1 
1 '-many'
1      Generate code for any architecture (PWR/PWRX/PPC).
1 
1 '-mregnames'
1      Allow symbolic names for registers.
1 
1 '-mno-regnames'
1      Do not allow symbolic names for registers.
1 
1 '-mrelocatable'
1      Support for GCC's -mrelocatable option.
1 
1 '-mrelocatable-lib'
1      Support for GCC's -mrelocatable-lib option.
1 
1 '-memb'
1      Set PPC_EMB bit in ELF flags.
1 
1 '-mlittle, -mlittle-endian, -le'
1      Generate code for a little endian machine.
1 
1 '-mbig, -mbig-endian, -be'
1      Generate code for a big endian machine.
1 
1 '-msolaris'
1      Generate code for Solaris.
1 
1 '-mno-solaris'
1      Do not generate code for Solaris.
1 
1 '-nops=COUNT'
1      If an alignment directive inserts more than COUNT nops, put a
1      branch at the beginning to skip execution of the nops.
1