as: Overview
1
1 1 Overview
1 **********
1
11 Here is a brief summary of how to invoke 'as'. For details, see ⇒
Command-Line Options Invoking.
1
1 as [-a[cdghlns][=FILE]] [-alternate] [-D]
1 [-compress-debug-sections] [-nocompress-debug-sections]
1 [-debug-prefix-map OLD=NEW]
1 [-defsym SYM=VAL] [-f] [-g] [-gstabs]
1 [-gstabs+] [-gdwarf-2] [-gdwarf-sections]
1 [-help] [-I DIR] [-J]
1 [-K] [-L] [-listing-lhs-width=NUM]
1 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
1 [-listing-cont-lines=NUM] [-keep-locals]
1 [-no-pad-sections]
1 [-o OBJFILE] [-R]
1 [-hash-size=NUM] [-reduce-memory-overheads]
1 [-statistics]
1 [-v] [-version] [-version]
1 [-W] [-warn] [-fatal-warnings] [-w] [-x]
1 [-Z] [@FILE]
1 [-sectname-subst] [-size-check=[error|warning]]
1 [-elf-stt-common=[no|yes]]
1 [-generate-missing-build-notes=[no|yes]]
1 [-target-help] [TARGET-OPTIONS]
1 [-|FILES ...]
1
1 _Target AArch64 options:_
1 [-EB|-EL]
1 [-mabi=ABI]
1
1 _Target Alpha options:_
1 [-mCPU]
1 [-mdebug | -no-mdebug]
1 [-replace | -noreplace]
1 [-relax] [-g] [-GSIZE]
1 [-F] [-32addr]
1
1 _Target ARC options:_
1 [-mcpu=CPU]
1 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
1 [-mcode-density]
1 [-mrelax]
1 [-EB|-EL]
1
1 _Target ARM options:_
1 [-mcpu=PROCESSOR[+EXTENSION...]]
1 [-march=ARCHITECTURE[+EXTENSION...]]
1 [-mfpu=FLOATING-POINT-FORMAT]
1 [-mfloat-abi=ABI]
1 [-meabi=VER]
1 [-mthumb]
1 [-EB|-EL]
1 [-mapcs-32|-mapcs-26|-mapcs-float|
1 -mapcs-reentrant]
1 [-mthumb-interwork] [-k]
1
1 _Target Blackfin options:_
1 [-mcpu=PROCESSOR[-SIREVISION]]
1 [-mfdpic]
1 [-mno-fdpic]
1 [-mnopic]
1
1 _Target CRIS options:_
1 [-underscore | -no-underscore]
1 [-pic] [-N]
1 [-emulation=criself | -emulation=crisaout]
1 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
1
1 _Target D10V options:_
1 [-O]
1
1 _Target D30V options:_
1 [-O|-n|-N]
1
1 _Target EPIPHANY options:_
1 [-mepiphany|-mepiphany16]
1
1 _Target H8/300 options:_
1 [-h-tick-hex]
1
1 _Target i386 options:_
1 [-32|-x32|-64] [-n]
1 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
1
1 _Target i960 options:_
1 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
1 -AKC|-AMC]
1 [-b] [-no-relax]
1
1 _Target IA-64 options:_
1 [-mconstant-gp|-mauto-pic]
1 [-milp32|-milp64|-mlp64|-mp64]
1 [-mle|mbe]
1 [-mtune=itanium1|-mtune=itanium2]
1 [-munwind-check=warning|-munwind-check=error]
1 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
1 [-x|-xexplicit] [-xauto] [-xdebug]
1
1 _Target IP2K options:_
1 [-mip2022|-mip2022ext]
1
1 _Target M32C options:_
1 [-m32c|-m16c] [-relax] [-h-tick-hex]
1
1 _Target M32R options:_
1 [-m32rx|-[no-]warn-explicit-parallel-conflicts|
1 -W[n]p]
1
1 _Target M680X0 options:_
1 [-l] [-m68000|-m68010|-m68020|...]
1
1 _Target M68HC11 options:_
1 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
1 [-mshort|-mlong]
1 [-mshort-double|-mlong-double]
1 [-force-long-branches] [-short-branches]
1 [-strict-direct-mode] [-print-insn-syntax]
1 [-print-opcodes] [-generate-example]
1
1 _Target MCORE options:_
1 [-jsri2bsr] [-sifilter] [-relax]
1 [-mcpu=[210|340]]
1
1 _Target Meta options:_
1 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU]
1 _Target MICROBLAZE options:_
1
1 _Target MIPS options:_
1 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
1 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
1 [-non_shared] [-xgot [-mvxworks-pic]
1 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
1 [-mfp64] [-mgp64] [-mfpxx]
1 [-modd-spreg] [-mno-odd-spreg]
1 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
1 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
1 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
1 [-mips64r3] [-mips64r5] [-mips64r6]
1 [-construct-floats] [-no-construct-floats]
1 [-mignore-branch-isa] [-mno-ignore-branch-isa]
1 [-mnan=ENCODING]
1 [-trap] [-no-break] [-break] [-no-trap]
1 [-mips16] [-no-mips16]
1 [-mmips16e2] [-mno-mips16e2]
1 [-mmicromips] [-mno-micromips]
1 [-msmartmips] [-mno-smartmips]
1 [-mips3d] [-no-mips3d]
1 [-mdmx] [-no-mdmx]
1 [-mdsp] [-mno-dsp]
1 [-mdspr2] [-mno-dspr2]
1 [-mdspr3] [-mno-dspr3]
1 [-mmsa] [-mno-msa]
1 [-mxpa] [-mno-xpa]
1 [-mmt] [-mno-mt]
1 [-mmcu] [-mno-mcu]
1 [-minsn32] [-mno-insn32]
1 [-mfix7000] [-mno-fix7000]
1 [-mfix-rm7000] [-mno-fix-rm7000]
1 [-mfix-vr4120] [-mno-fix-vr4120]
1 [-mfix-vr4130] [-mno-fix-vr4130]
1 [-mdebug] [-no-mdebug]
1 [-mpdr] [-mno-pdr]
1
1 _Target MMIX options:_
1 [-fixed-special-register-names] [-globalize-symbols]
1 [-gnu-syntax] [-relax] [-no-predefined-symbols]
1 [-no-expand] [-no-merge-gregs] [-x]
1 [-linker-allocated-gregs]
1
1 _Target Nios II options:_
1 [-relax-all] [-relax-section] [-no-relax]
1 [-EB] [-EL]
1
1 _Target NDS32 options:_
1 [-EL] [-EB] [-O] [-Os] [-mcpu=CPU]
1 [-misa=ISA] [-mabi=ABI] [-mall-ext]
1 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
1 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
1 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
1 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
1 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
1 [-mb2bb]
1
1 _Target PDP11 options:_
1 [-mpic|-mno-pic] [-mall] [-mno-extensions]
1 [-mEXTENSION|-mno-EXTENSION]
1 [-mCPU] [-mMACHINE]
1
1 _Target picoJava options:_
1 [-mb|-me]
1
1 _Target PowerPC options:_
1 [-a32|-a64]
1 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
1 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
1 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
1 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
1 -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
1 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
1 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
1 [-mregnames|-mno-regnames]
1 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
1 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
1 [-msolaris|-mno-solaris]
1 [-nops=COUNT]
1
1 _Target PRU options:_
1 [-link-relax]
1 [-mnolink-relax]
1 [-mno-warn-regname-label]
1
1 _Target RISC-V options:_
1 [-fpic|-fPIC|-fno-pic]
1 [-march=ISA]
1 [-mabi=ABI]
1
1 _Target RL78 options:_
1 [-mg10]
1 [-m32bit-doubles|-m64bit-doubles]
1
1 _Target RX options:_
1 [-mlittle-endian|-mbig-endian]
1 [-m32bit-doubles|-m64bit-doubles]
1 [-muse-conventional-section-names]
1 [-msmall-data-limit]
1 [-mpid]
1 [-mrelax]
1 [-mint-register=NUMBER]
1 [-mgcc-abi|-mrx-abi]
1
1 _Target s390 options:_
1 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
1 [-mregnames|-mno-regnames]
1 [-mwarn-areg-zero]
1
1 _Target SCORE options:_
1 [-EB][-EL][-FIXDD][-NWARN]
1 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
1 [-march=score7][-march=score3]
1 [-USE_R1][-KPIC][-O0][-G NUM][-V]
1
1 _Target SPARC options:_
1 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
1 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
1 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
1 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
1 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
1 -Asparcvisr|-Asparc5]
1 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
1 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
1 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
1 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
1 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
1 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
1 -bump]
1 [-32|-64]
1 [-enforce-aligned-data][-dcti-couples-detect]
1
1 _Target TIC54X options:_
1 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
1 [-merrors-to-file <FILENAME>|-me <FILENAME>]
1
1 _Target TIC6X options:_
1 [-march=ARCH] [-mbig-endian|-mlittle-endian]
1 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
1 [-mpic|-mno-pic]
1
1 _Target TILE-Gx options:_
1 [-m32|-m64][-EB][-EL]
1
1 _Target Visium options:_
1 [-mtune=ARCH]
1
1 _Target Xtensa options:_
1 [-[no-]text-section-literals] [-[no-]auto-litpools]
1 [-[no-]absolute-literals]
1 [-[no-]target-align] [-[no-]longcalls]
1 [-[no-]transform]
1 [-rename-section OLDNAME=NEWNAME]
1 [-[no-]trampolines]
1
1 _Target Z80 options:_
1 [-z80] [-r800]
1 [ -ignore-undocumented-instructions] [-Wnud]
1 [ -ignore-unportable-instructions] [-Wnup]
1 [ -warn-undocumented-instructions] [-Wud]
1 [ -warn-unportable-instructions] [-Wup]
1 [ -forbid-undocumented-instructions] [-Fud]
1 [ -forbid-unportable-instructions] [-Fup]
1
1
1
1 '@FILE'
1 Read command-line options from FILE. The options read are inserted
1 in place of the original @FILE option. If FILE does not exist, or
1 cannot be read, then the option will be treated literally, and not
1 removed.
1
1 Options in FILE are separated by whitespace. A whitespace
1 character may be included in an option by surrounding the entire
1 option in either single or double quotes. Any character (including
1 a backslash) may be included by prefixing the character to be
1 included with a backslash. The FILE may itself contain additional
1 @FILE options; any such options will be processed recursively.
1
1 '-a[cdghlmns]'
1 Turn on listings, in any of a variety of ways:
1
1 '-ac'
1 omit false conditionals
1
1 '-ad'
1 omit debugging directives
1
1 '-ag'
1 include general information, like as version and options
1 passed
1
1 '-ah'
1 include high-level source
1
1 '-al'
1 include assembly
1
1 '-am'
1 include macro expansions
1
1 '-an'
1 omit forms processing
1
1 '-as'
1 include symbols
1
1 '=file'
1 set the name of the listing file
1
1 You may combine these options; for example, use '-aln' for assembly
1 listing without forms processing. The '=file' option, if used,
1 must be the last one. By itself, '-a' defaults to '-ahls'.
1
1 '--alternate'
1 Begin in alternate macro mode. ⇒'.altmacro' Altmacro.
1
1 '--compress-debug-sections'
1 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
1 the ELF ABI. The resulting object file may not be compatible with
1 older linkers and object file utilities. Note if compression would
1 make a given section _larger_ then it is not compressed.
1
1 '--compress-debug-sections=none'
1 '--compress-debug-sections=zlib'
1 '--compress-debug-sections=zlib-gnu'
1 '--compress-debug-sections=zlib-gabi'
1 These options control how DWARF debug sections are compressed.
1 '--compress-debug-sections=none' is equivalent to
1 '--nocompress-debug-sections'. '--compress-debug-sections=zlib'
1 and '--compress-debug-sections=zlib-gabi' are equivalent to
1 '--compress-debug-sections'. '--compress-debug-sections=zlib-gnu'
1 compresses DWARF debug sections using zlib. The debug sections are
1 renamed to begin with '.zdebug'. Note if compression would make a
1 given section _larger_ then it is not compressed nor renamed.
1
1 '--nocompress-debug-sections'
1 Do not compress DWARF debug sections. This is usually the default
1 for all targets except the x86/x86_64, but a configure time option
1 can be used to override this.
1
1 '-D'
1 Ignored. This option is accepted for script compatibility with
1 calls to other assemblers.
1
1 '--debug-prefix-map OLD=NEW'
1 When assembling files in directory 'OLD', record debugging
1 information describing them as in 'NEW' instead.
1
1 '--defsym SYM=VALUE'
1 Define the symbol SYM to be VALUE before assembling the input file.
1 VALUE must be an integer constant. As in C, a leading '0x'
1 indicates a hexadecimal value, and a leading '0' indicates an octal
1 value. The value of the symbol can be overridden inside a source
1 file via the use of a '.set' pseudo-op.
1
1 '-f'
1 "fast"--skip whitespace and comment preprocessing (assume source is
1 compiler output).
1
1 '-g'
1 '--gen-debug'
1 Generate debugging information for each assembler source line using
1 whichever debug format is preferred by the target. This currently
1 means either STABS, ECOFF or DWARF2.
1
1 '--gstabs'
1 Generate stabs debugging information for each assembler line. This
1 may help debugging assembler code, if the debugger can handle it.
1
1 '--gstabs+'
1 Generate stabs debugging information for each assembler line, with
1 GNU extensions that probably only gdb can handle, and that could
1 make other debuggers crash or refuse to read your program. This
1 may help debugging assembler code. Currently the only GNU
1 extension is the location of the current working directory at
1 assembling time.
1
1 '--gdwarf-2'
1 Generate DWARF2 debugging information for each assembler line.
1 This may help debugging assembler code, if the debugger can handle
1 it. Note--this option is only supported by some targets, not all
1 of them.
1
1 '--gdwarf-sections'
1 Instead of creating a .debug_line section, create a series of
1 .debug_line.FOO sections where FOO is the name of the corresponding
1 code section. For example a code section called .TEXT.FUNC will
1 have its dwarf line number information placed into a section called
1 .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT
1 then debug line section will still be called just .DEBUG_LINE
1 without any suffix.
1
1 '--size-check=error'
1 '--size-check=warning'
1 Issue an error or warning for invalid ELF .size directive.
1
1 '--elf-stt-common=no'
1 '--elf-stt-common=yes'
1 These options control whether the ELF assembler should generate
1 common symbols with the 'STT_COMMON' type. The default can be
1 controlled by a configure option '--enable-elf-stt-common'.
1
1 '--generate-missing-build-notes=yes'
1 '--generate-missing-build-notes=no'
1 These options control whether the ELF assembler should generate GNU
1 Build attribute notes if none are present in the input sources.
1 The default can be controlled by the
1 '--enable-generate-build-notes' configure option.
1
1 '--help'
1 Print a summary of the command line options and exit.
1
1 '--target-help'
1 Print a summary of all target specific options and exit.
1
1 '-I DIR'
1 Add directory DIR to the search list for '.include' directives.
1
1 '-J'
1 Don't warn about signed overflow.
1
1 '-K'
1 Issue warnings when difference tables altered for long
1 displacements.
1
1 '-L'
1 '--keep-locals'
1 Keep (in the symbol table) local symbols. These symbols start with
1 system-specific local label prefixes, typically '.L' for ELF
11 systems or 'L' for traditional a.out systems. ⇒Symbol
Names.
1
1 '--listing-lhs-width=NUMBER'
1 Set the maximum width, in words, of the output data column for an
1 assembler listing to NUMBER.
1
1 '--listing-lhs-width2=NUMBER'
1 Set the maximum width, in words, of the output data column for
1 continuation lines in an assembler listing to NUMBER.
1
1 '--listing-rhs-width=NUMBER'
1 Set the maximum width of an input source line, as displayed in a
1 listing, to NUMBER bytes.
1
1 '--listing-cont-lines=NUMBER'
1 Set the maximum number of lines printed in a listing for a single
1 line of input to NUMBER + 1.
1
1 '--no-pad-sections'
1 Stop the assembler for padding the ends of output sections to the
1 alignment of that section. The default is to pad the sections, but
1 this can waste space which might be needed on targets which have
1 tight memory constraints.
1
1 '-o OBJFILE'
1 Name the object-file output from 'as' OBJFILE.
1
1 '-R'
1 Fold the data section into the text section.
1
1 '--hash-size=NUMBER'
1 Set the default size of GAS's hash tables to a prime number close
1 to NUMBER. Increasing this value can reduce the length of time it
1 takes the assembler to perform its tasks, at the expense of
1 increasing the assembler's memory requirements. Similarly reducing
1 this value can reduce the memory requirements at the expense of
1 speed.
1
1 '--reduce-memory-overheads'
1 This option reduces GAS's memory requirements, at the expense of
1 making the assembly processes slower. Currently this switch is a
1 synonym for '--hash-size=4051', but in the future it may have other
1 effects as well.
1
1 '--sectname-subst'
1 Honor substitution sequences in section names. *Note'.section
1 NAME': Section Name Substitutions.
1
1 '--statistics'
1 Print the maximum space (in bytes) and total time (in seconds) used
1 by assembly.
1
1 '--strip-local-absolute'
1 Remove local absolute symbols from the outgoing symbol table.
1
1 '-v'
1 '-version'
1 Print the 'as' version.
1
1 '--version'
1 Print the 'as' version and exit.
1
1 '-W'
1 '--no-warn'
1 Suppress warning messages.
1
1 '--fatal-warnings'
1 Treat warnings as errors.
1
1 '--warn'
1 Don't suppress warning messages or treat them as errors.
1
1 '-w'
1 Ignored.
1
1 '-x'
1 Ignored.
1
1 '-Z'
1 Generate an object file even after errors.
1
1 '-- | FILES ...'
1 Standard input, or source files to assemble.
1
1 ⇒AArch64 Options, for the options available when as is
1 configured for the 64-bit mode of the ARM Architecture (AArch64).
1
1 ⇒Alpha Options, for the options available when as is
1 configured for an Alpha processor.
1
1 The following options are available when as is configured for an ARC
1 processor.
1
1 '-mcpu=CPU'
1 This option selects the core processor variant.
1 '-EB | -EL'
1 Select either big-endian (-EB) or little-endian (-EL) output.
1 '-mcode-density'
1 Enable Code Density extenssion instructions.
1
1 The following options are available when as is configured for the ARM
1 processor family.
1
1 '-mcpu=PROCESSOR[+EXTENSION...]'
1 Specify which ARM processor variant is the target.
1 '-march=ARCHITECTURE[+EXTENSION...]'
1 Specify which ARM architecture variant is used by the target.
1 '-mfpu=FLOATING-POINT-FORMAT'
1 Select which Floating Point architecture is the target.
1 '-mfloat-abi=ABI'
1 Select which floating point ABI is in use.
1 '-mthumb'
1 Enable Thumb only instruction decoding.
1 '-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
1 Select which procedure calling convention is in use.
1 '-EB | -EL'
1 Select either big-endian (-EB) or little-endian (-EL) output.
1 '-mthumb-interwork'
1 Specify that the code has been generated with interworking between
1 Thumb and ARM code in mind.
1 '-mccs'
1 Turns on CodeComposer Studio assembly syntax compatibility mode.
1 '-k'
1 Specify that PIC code has been generated.
1
1 ⇒Blackfin Options, for the options available when as is
1 configured for the Blackfin processor family.
1
1 See the info pages for documentation of the CRIS-specific options.
1
1 The following options are available when as is configured for a D10V
1 processor.
1 '-O'
1 Optimize output by parallelizing instructions.
1
1 The following options are available when as is configured for a D30V
1 processor.
1 '-O'
1 Optimize output by parallelizing instructions.
1
1 '-n'
1 Warn when nops are generated.
1
1 '-N'
1 Warn when a nop after a 32-bit multiply instruction is generated.
1
1 The following options are available when as is configured for the
1 Adapteva EPIPHANY series.
1
1 ⇒Epiphany Options, for the options available when as is
1 configured for an Epiphany processor.
1
1 ⇒i386-Options, for the options available when as is configured
1 for an i386 processor.
1
1 The following options are available when as is configured for the
1 Intel 80960 processor.
1
1 '-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
1 Specify which variant of the 960 architecture is the target.
1
1 '-b'
1 Add code to collect statistics about branches taken.
1
1 '-no-relax'
1 Do not alter compare-and-branch instructions for long
1 displacements; error if necessary.
1
1 The following options are available when as is configured for the
1 Ubicom IP2K series.
1
1 '-mip2022ext'
1 Specifies that the extended IP2022 instructions are allowed.
1
1 '-mip2022'
1 Restores the default behaviour, which restricts the permitted
1 instructions to just the basic IP2022 ones.
1
1 The following options are available when as is configured for the
1 Renesas M32C and M16C processors.
1
1 '-m32c'
1 Assemble M32C instructions.
1
1 '-m16c'
1 Assemble M16C instructions (the default).
1
1 '-relax'
1 Enable support for link-time relaxations.
1
1 '-h-tick-hex'
1 Support H'00 style hex constants in addition to 0x00 style.
1
1 The following options are available when as is configured for the
1 Renesas M32R (formerly Mitsubishi M32R) series.
1
1 '--m32rx'
1 Specify which processor in the M32R family is the target. The
1 default is normally the M32R, but this option changes it to the
1 M32RX.
1
1 '--warn-explicit-parallel-conflicts or --Wp'
1 Produce warning messages when questionable parallel constructs are
1 encountered.
1
1 '--no-warn-explicit-parallel-conflicts or --Wnp'
1 Do not produce warning messages when questionable parallel
1 constructs are encountered.
1
1 The following options are available when as is configured for the
1 Motorola 68000 series.
1
1 '-l'
1 Shorten references to undefined symbols, to one word instead of
1 two.
1
1 '-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
1 '| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
1 '| -m68333 | -m68340 | -mcpu32 | -m5200'
1 Specify what processor in the 68000 family is the target. The
1 default is normally the 68020, but this can be changed at
1 configuration time.
1
1 '-m68881 | -m68882 | -mno-68881 | -mno-68882'
1 The target machine does (or does not) have a floating-point
1 coprocessor. The default is to assume a coprocessor for 68020,
1 68030, and cpu32. Although the basic 68000 is not compatible with
1 the 68881, a combination of the two can be specified, since it's
1 possible to do emulation of the coprocessor instructions with the
1 main processor.
1
1 '-m68851 | -mno-68851'
1 The target machine does (or does not) have a memory-management unit
1 coprocessor. The default is to assume an MMU for 68020 and up.
1
1 ⇒Nios II Options, for the options available when as is
1 configured for an Altera Nios II processor.
1
1 For details about the PDP-11 machine dependent features options, see
1 ⇒PDP-11-Options.
1
1 '-mpic | -mno-pic'
1 Generate position-independent (or position-dependent) code. The
1 default is '-mpic'.
1
1 '-mall'
1 '-mall-extensions'
1 Enable all instruction set extensions. This is the default.
1
1 '-mno-extensions'
1 Disable all instruction set extensions.
1
1 '-mEXTENSION | -mno-EXTENSION'
1 Enable (or disable) a particular instruction set extension.
1
1 '-mCPU'
1 Enable the instruction set extensions supported by a particular
1 CPU, and disable all other extensions.
1
1 '-mMACHINE'
1 Enable the instruction set extensions supported by a particular
1 machine model, and disable all other extensions.
1
1 The following options are available when as is configured for a
1 picoJava processor.
1
1 '-mb'
1 Generate "big endian" format output.
1
1 '-ml'
1 Generate "little endian" format output.
1
1 ⇒PRU Options, for the options available when as is configured
1 for a PRU processor.
1
1 The following options are available when as is configured for the
1 Motorola 68HC11 or 68HC12 series.
1
1 '-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg'
1 Specify what processor is the target. The default is defined by
1 the configuration option when building the assembler.
1
1 '--xgate-ramoffset'
1 Instruct the linker to offset RAM addresses from S12X address space
1 into XGATE address space.
1
1 '-mshort'
1 Specify to use the 16-bit integer ABI.
1
1 '-mlong'
1 Specify to use the 32-bit integer ABI.
1
1 '-mshort-double'
1 Specify to use the 32-bit double ABI.
1
1 '-mlong-double'
1 Specify to use the 64-bit double ABI.
1
1 '--force-long-branches'
1 Relative branches are turned into absolute ones. This concerns
1 conditional branches, unconditional branches and branches to a sub
1 routine.
1
1 '-S | --short-branches'
1 Do not turn relative branches into absolute ones when the offset is
1 out of range.
1
1 '--strict-direct-mode'
1 Do not turn the direct addressing mode into extended addressing
1 mode when the instruction does not support direct addressing mode.
1
1 '--print-insn-syntax'
1 Print the syntax of instruction in case of error.
1
1 '--print-opcodes'
1 Print the list of instructions with syntax and then exit.
1
1 '--generate-example'
1 Print an example of instruction for each possible instruction and
1 then exit. This option is only useful for testing 'as'.
1
1 The following options are available when 'as' is configured for the
1 SPARC architecture:
1
1 '-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
1 '-Av8plus | -Av8plusa | -Av9 | -Av9a'
1 Explicitly select a variant of the SPARC architecture.
1
1 '-Av8plus' and '-Av8plusa' select a 32 bit environment. '-Av9' and
1 '-Av9a' select a 64 bit environment.
1
1 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with
1 UltraSPARC extensions.
1
1 '-xarch=v8plus | -xarch=v8plusa'
1 For compatibility with the Solaris v9 assembler. These options are
1 equivalent to -Av8plus and -Av8plusa, respectively.
1
1 '-bump'
1 Warn when the assembler switches to another architecture.
1
1 The following options are available when as is configured for the
1 'c54x architecture.
1
1 '-mfar-mode'
1 Enable extended addressing mode. All addresses and relocations
1 will assume extended addressing (usually 23 bits).
1 '-mcpu=CPU_VERSION'
1 Sets the CPU version being compiled for.
1 '-merrors-to-file FILENAME'
1 Redirect error output to a file, for broken systems which don't
1 support such behaviour in the shell.
1
1 The following options are available when as is configured for a MIPS
1 processor.
1
1 '-G NUM'
1 This option sets the largest size of an object that can be
1 referenced implicitly with the 'gp' register. It is only accepted
1 for targets that use ECOFF format, such as a DECstation running
1 Ultrix. The default value is 8.
1
1 '-EB'
1 Generate "big endian" format output.
1
1 '-EL'
1 Generate "little endian" format output.
1
1 '-mips1'
1 '-mips2'
1 '-mips3'
1 '-mips4'
1 '-mips5'
1 '-mips32'
1 '-mips32r2'
1 '-mips32r3'
1 '-mips32r5'
1 '-mips32r6'
1 '-mips64'
1 '-mips64r2'
1 '-mips64r3'
1 '-mips64r5'
1 '-mips64r6'
1 Generate code for a particular MIPS Instruction Set Architecture
1 level. '-mips1' is an alias for '-march=r3000', '-mips2' is an
1 alias for '-march=r6000', '-mips3' is an alias for '-march=r4000'
1 and '-mips4' is an alias for '-march=r8000'. '-mips5', '-mips32',
1 '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', '-mips64',
1 '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' correspond
1 to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3,
1 MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2,
1 MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA
1 processors, respectively.
1
1 '-march=CPU'
1 Generate code for a particular MIPS CPU.
1
1 '-mtune=CPU'
1 Schedule and tune for a particular MIPS CPU.
1
1 '-mfix7000'
1 '-mno-fix7000'
1 Cause nops to be inserted if the read of the destination register
1 of an mfhi or mflo instruction occurs in the following two
1 instructions.
1
1 '-mfix-rm7000'
1 '-mno-fix-rm7000'
1 Cause nops to be inserted if a dmult or dmultu instruction is
1 followed by a load instruction.
1
1 '-mdebug'
1 '-no-mdebug'
1 Cause stabs-style debugging output to go into an ECOFF-style
1 .mdebug section instead of the standard ELF .stabs sections.
1
1 '-mpdr'
1 '-mno-pdr'
1 Control generation of '.pdr' sections.
1
1 '-mgp32'
1 '-mfp32'
1 The register sizes are normally inferred from the ISA and ABI, but
1 these flags force a certain group of registers to be treated as 32
1 bits wide at all times. '-mgp32' controls the size of
1 general-purpose registers and '-mfp32' controls the size of
1 floating-point registers.
1
1 '-mgp64'
1 '-mfp64'
1 The register sizes are normally inferred from the ISA and ABI, but
1 these flags force a certain group of registers to be treated as 64
1 bits wide at all times. '-mgp64' controls the size of
1 general-purpose registers and '-mfp64' controls the size of
1 floating-point registers.
1
1 '-mfpxx'
1 The register sizes are normally inferred from the ISA and ABI, but
1 using this flag in combination with '-mabi=32' enables an ABI
1 variant which will operate correctly with floating-point registers
1 which are 32 or 64 bits wide.
1
1 '-modd-spreg'
1 '-mno-odd-spreg'
1 Enable use of floating-point operations on odd-numbered
1 single-precision registers when supported by the ISA. '-mfpxx'
1 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'.
1
1 '-mips16'
1 '-no-mips16'
1 Generate code for the MIPS 16 processor. This is equivalent to
1 putting '.module mips16' at the start of the assembly file.
1 '-no-mips16' turns off this option.
1
1 '-mmips16e2'
1 '-mno-mips16e2'
1 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1 equivalent to putting '.module mips16e2' at the start of the
1 assembly file. '-mno-mips16e2' turns off this option.
1
1 '-mmicromips'
1 '-mno-micromips'
1 Generate code for the microMIPS processor. This is equivalent to
1 putting '.module micromips' at the start of the assembly file.
1 '-mno-micromips' turns off this option. This is equivalent to
1 putting '.module nomicromips' at the start of the assembly file.
1
1 '-msmartmips'
1 '-mno-smartmips'
1 Enables the SmartMIPS extension to the MIPS32 instruction set.
1 This is equivalent to putting '.module smartmips' at the start of
1 the assembly file. '-mno-smartmips' turns off this option.
1
1 '-mips3d'
1 '-no-mips3d'
1 Generate code for the MIPS-3D Application Specific Extension. This
1 tells the assembler to accept MIPS-3D instructions. '-no-mips3d'
1 turns off this option.
1
1 '-mdmx'
1 '-no-mdmx'
1 Generate code for the MDMX Application Specific Extension. This
1 tells the assembler to accept MDMX instructions. '-no-mdmx' turns
1 off this option.
1
1 '-mdsp'
1 '-mno-dsp'
1 Generate code for the DSP Release 1 Application Specific Extension.
1 This tells the assembler to accept DSP Release 1 instructions.
1 '-mno-dsp' turns off this option.
1
1 '-mdspr2'
1 '-mno-dspr2'
1 Generate code for the DSP Release 2 Application Specific Extension.
1 This option implies '-mdsp'. This tells the assembler to accept
1 DSP Release 2 instructions. '-mno-dspr2' turns off this option.
1
1 '-mdspr3'
1 '-mno-dspr3'
1 Generate code for the DSP Release 3 Application Specific Extension.
1 This option implies '-mdsp' and '-mdspr2'. This tells the
1 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns
1 off this option.
1
1 '-mmsa'
1 '-mno-msa'
1 Generate code for the MIPS SIMD Architecture Extension. This tells
1 the assembler to accept MSA instructions. '-mno-msa' turns off
1 this option.
1
1 '-mxpa'
1 '-mno-xpa'
1 Generate code for the MIPS eXtended Physical Address (XPA)
1 Extension. This tells the assembler to accept XPA instructions.
1 '-mno-xpa' turns off this option.
1
1 '-mmt'
1 '-mno-mt'
1 Generate code for the MT Application Specific Extension. This
1 tells the assembler to accept MT instructions. '-mno-mt' turns off
1 this option.
1
1 '-mmcu'
1 '-mno-mcu'
1 Generate code for the MCU Application Specific Extension. This
1 tells the assembler to accept MCU instructions. '-mno-mcu' turns
1 off this option.
1
1 '-minsn32'
1 '-mno-insn32'
1 Only use 32-bit instruction encodings when generating code for the
1 microMIPS processor. This option inhibits the use of any 16-bit
1 instructions. This is equivalent to putting '.set insn32' at the
1 start of the assembly file. '-mno-insn32' turns off this option.
1 This is equivalent to putting '.set noinsn32' at the start of the
1 assembly file. By default '-mno-insn32' is selected, allowing all
1 instructions to be used.
1
1 '--construct-floats'
1 '--no-construct-floats'
1 The '--no-construct-floats' option disables the construction of
1 double width floating point constants by loading the two halves of
1 the value into the two single width floating point registers that
1 make up the double width register. By default '--construct-floats'
1 is selected, allowing construction of these floating point
1 constants.
1
1 '--relax-branch'
1 '--no-relax-branch'
1 The '--relax-branch' option enables the relaxation of out-of-range
1 branches. By default '--no-relax-branch' is selected, causing any
1 out-of-range branches to produce an error.
1
1 '-mignore-branch-isa'
1 '-mno-ignore-branch-isa'
1 Ignore branch checks for invalid transitions between ISA modes.
1 The semantics of branches does not provide for an ISA mode switch,
1 so in most cases the ISA mode a branch has been encoded for has to
1 be the same as the ISA mode of the branch's target label.
1 Therefore GAS has checks implemented that verify in branch assembly
1 that the two ISA modes match. '-mignore-branch-isa' disables these
1 checks. By default '-mno-ignore-branch-isa' is selected, causing
1 any invalid branch requiring a transition between ISA modes to
1 produce an error.
1
1 '-mnan=ENCODING'
1 Select between the IEEE 754-2008 ('-mnan=2008') or the legacy
1 ('-mnan=legacy') NaN encoding format. The latter is the default.
1
1 '--emulation=NAME'
1 This option was formerly used to switch between ELF and ECOFF
1 output on targets like IRIX 5 that supported both. MIPS ECOFF
1 support was removed in GAS 2.24, so the option now serves little
1 purpose. It is retained for backwards compatibility.
1
1 The available configuration names are: 'mipself', 'mipslelf' and
1 'mipsbelf'. Choosing 'mipself' now has no effect, since the output
1 is always ELF. 'mipslelf' and 'mipsbelf' select little- and
1 big-endian output respectively, but '-EL' and '-EB' are now the
1 preferred options instead.
1
1 '-nocpp'
1 'as' ignores this option. It is accepted for compatibility with
1 the native tools.
1
1 '--trap'
1 '--no-trap'
1 '--break'
1 '--no-break'
1 Control how to deal with multiplication overflow and division by
1 zero. '--trap' or '--no-break' (which are synonyms) take a trap
1 exception (and only work for Instruction Set Architecture level 2
1 and higher); '--break' or '--no-trap' (also synonyms, and the
1 default) take a break exception.
1
1 '-n'
1 When this option is used, 'as' will issue a warning every time it
1 generates a nop instruction from a macro.
1
1 The following options are available when as is configured for an
1 MCore processor.
1
1 '-jsri2bsr'
1 '-nojsri2bsr'
1 Enable or disable the JSRI to BSR transformation. By default this
1 is enabled. The command line option '-nojsri2bsr' can be used to
1 disable it.
1
1 '-sifilter'
1 '-nosifilter'
1 Enable or disable the silicon filter behaviour. By default this is
1 disabled. The default can be overridden by the '-sifilter' command
1 line option.
1
1 '-relax'
1 Alter jump instructions for long displacements.
1
1 '-mcpu=[210|340]'
1 Select the cpu type on the target hardware. This controls which
1 instructions can be assembled.
1
1 '-EB'
1 Assemble for a big endian target.
1
1 '-EL'
1 Assemble for a little endian target.
1
1 ⇒Meta Options, for the options available when as is configured
1 for a Meta processor.
1
1 See the info pages for documentation of the MMIX-specific options.
1
1 ⇒NDS32 Options, for the options available when as is
1 configured for a NDS32 processor.
1
1 ⇒PowerPC-Opts, for the options available when as is configured
1 for a PowerPC processor.
1
1 ⇒RISC-V-Options, for the options available when as is
1 configured for a RISC-V processor.
1
1 See the info pages for documentation of the RX-specific options.
1
1 The following options are available when as is configured for the
1 s390 processor family.
1
1 '-m31'
1 '-m64'
1 Select the word size, either 31/32 bits or 64 bits.
1 '-mesa'
1 '-mzarch'
1 Select the architecture mode, either the Enterprise System
1 Architecture (esa) or the z/Architecture mode (zarch).
1 '-march=PROCESSOR'
1 Specify which s390 processor variant is the target, 'g5' (or
1 'arch3'), 'g6', 'z900' (or 'arch5'), 'z990' (or 'arch6'), 'z9-109',
1 'z9-ec' (or 'arch7'), 'z10' (or 'arch8'), 'z196' (or 'arch9'),
1 'zEC12' (or 'arch10'), 'z13' (or 'arch11'), or 'z14' (or 'arch12').
1 '-mregnames'
1 '-mno-regnames'
1 Allow or disallow symbolic names for registers.
1 '-mwarn-areg-zero'
1 Warn whenever the operand for a base or index register has been
1 specified but evaluates to zero.
1
1 ⇒TIC6X Options, for the options available when as is
1 configured for a TMS320C6000 processor.
1
1 ⇒TILE-Gx Options, for the options available when as is
1 configured for a TILE-Gx processor.
1
1 ⇒Visium Options, for the options available when as is
1 configured for a Visium processor.
1
1 ⇒Xtensa Options, for the options available when as is
1 configured for an Xtensa processor.
1
1 The following options are available when as is configured for a Z80
1 family processor.
1 '-z80'
1 Assemble for Z80 processor.
1 '-r800'
1 Assemble for R800 processor.
1 '-ignore-undocumented-instructions'
1 '-Wnud'
1 Assemble undocumented Z80 instructions that also work on R800
1 without warning.
1 '-ignore-unportable-instructions'
1 '-Wnup'
1 Assemble all undocumented Z80 instructions without warning.
1 '-warn-undocumented-instructions'
1 '-Wud'
1 Issue a warning for undocumented Z80 instructions that also work on
1 R800.
1 '-warn-unportable-instructions'
1 '-Wup'
1 Issue a warning for undocumented Z80 instructions that do not work
1 on R800.
1 '-forbid-undocumented-instructions'
1 '-Fud'
1 Treat all undocumented instructions as errors.
1 '-forbid-unportable-instructions'
1 '-Fup'
1 Treat undocumented Z80 instructions that do not work on R800 as
1 errors.
1
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