as: Opcodes for i860
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1 9.16.4 i860 Opcodes
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1 All of the Intel i860XR and i860XP machine instructions are supported.
1 Please see either _i860 Microprocessor Programmer's Reference Manual_ or
1 _i860 Microprocessor Architecture_ for more information.
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1 9.16.4.1 Other instruction support (pseudo-instructions)
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1 For compatibility with some other i860 assemblers, a number of
1 pseudo-instructions are supported. While these are supported, they are
1 a very undesirable feature that should be avoided - in particular, when
1 they result in an expansion to multiple actual i860 instructions. Below
1 are the pseudo-instructions that result in expansions.
1 * Load large immediate into general register:
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1 The pseudo-instruction 'mov imm,%rn' (where the immediate does not
1 fit within a signed 16-bit field) will be expanded into:
1 orh large_imm@h,%r0,%rn
1 or large_imm@l,%rn,%rn
1 * Load/store with relocatable address expression:
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1 For example, the pseudo-instruction 'ld.b addr_exp(%rx),%rn' will
1 be expanded into:
1 orh addr_exp@ha,%rx,%r31
1 ld.l addr_exp@l(%r31),%rn
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1 The analogous expansions apply to 'ld.x, st.x, fld.x, pfld.x,
1 fst.x', and 'pst.x' as well.
1 * Signed large immediate with add/subtract:
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1 If any of the arithmetic operations 'adds, addu, subs, subu' are
1 used with an immediate larger than 16-bits (signed), then they will
1 be expanded. For instance, the pseudo-instruction 'adds
1 large_imm,%rx,%rn' expands to:
1 orh large_imm@h,%r0,%r31
1 or large_imm@l,%r31,%r31
1 adds %r31,%rx,%rn
1 * Unsigned large immediate with logical operations:
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1 Logical operations ('or, andnot, or, xor') also result in
1 expansions. The pseudo-instruction 'or large_imm,%rx,%rn' results
1 in:
1 orh large_imm@h,%rx,%r31
1 or large_imm@l,%r31,%rn
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1 Similarly for the others, except for 'and' which expands to:
1 andnot (-1 - large_imm)@h,%rx,%r31
1 andnot (-1 - large_imm)@l,%r31,%rn
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