as: MIPS Options
1
1 9.27.1 Assembler options
1 ------------------------
1
1 The MIPS configurations of GNU 'as' support these special options:
1
1 '-G NUM'
1 Set the "small data" limit to N bytes. The default limit is 8
11 bytes. ⇒Controlling the use of small data accesses MIPS
Small Data.
1
1 '-EB'
1 '-EL'
1 Any MIPS configuration of 'as' can select big-endian or
1 little-endian output at run time (unlike the other GNU development
1 tools, which must be configured for one or the other). Use '-EB'
1 to select big-endian output, and '-EL' for little-endian.
1
1 '-KPIC'
1 Generate SVR4-style PIC. This option tells the assembler to
1 generate SVR4-style position-independent macro expansions. It also
1 tells the assembler to mark the output file as PIC.
1
1 '-mvxworks-pic'
1 Generate VxWorks PIC. This option tells the assembler to generate
1 VxWorks-style position-independent macro expansions.
1
1 '-mips1'
1 '-mips2'
1 '-mips3'
1 '-mips4'
1 '-mips5'
1 '-mips32'
1 '-mips32r2'
1 '-mips32r3'
1 '-mips32r5'
1 '-mips32r6'
1 '-mips64'
1 '-mips64r2'
1 '-mips64r3'
1 '-mips64r5'
1 '-mips64r6'
1 Generate code for a particular MIPS Instruction Set Architecture
1 level. '-mips1' corresponds to the R2000 and R3000 processors,
1 '-mips2' to the R6000 processor, '-mips3' to the R4000 processor,
1 and '-mips4' to the R8000 and R10000 processors. '-mips5',
1 '-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6',
1 '-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6'
1 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32
1 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64
1 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6
1 ISA processors, respectively. You can also switch instruction sets
11 during the assembly; see ⇒Directives to override the ISA
level MIPS ISA.
1
1 '-mgp32'
1 '-mfp32'
1 Some macros have different expansions for 32-bit and 64-bit
1 registers. The register sizes are normally inferred from the ISA
1 and ABI, but these flags force a certain group of registers to be
1 treated as 32 bits wide at all times. '-mgp32' controls the size
1 of general-purpose registers and '-mfp32' controls the size of
1 floating-point registers.
1
1 The '.set gp=32' and '.set fp=32' directives allow the size of
1 registers to be changed for parts of an object. The default value
1 is restored by '.set gp=default' and '.set fp=default'.
1
1 On some MIPS variants there is a 32-bit mode flag; when this flag
1 is set, 64-bit instructions generate a trap. Also, some 32-bit
1 OSes only save the 32-bit registers on a context switch, so it is
1 essential never to use the 64-bit registers.
1
1 '-mgp64'
1 '-mfp64'
1 Assume that 64-bit registers are available. This is provided in
1 the interests of symmetry with '-mgp32' and '-mfp32'.
1
1 The '.set gp=64' and '.set fp=64' directives allow the size of
1 registers to be changed for parts of an object. The default value
1 is restored by '.set gp=default' and '.set fp=default'.
1
1 '-mfpxx'
1 Make no assumptions about whether 32-bit or 64-bit floating-point
1 registers are available. This is provided to support having
1 modules compatible with either '-mfp32' or '-mfp64'. This option
1 can only be used with MIPS II and above.
1
1 The '.set fp=xx' directive allows a part of an object to be marked
1 as not making assumptions about 32-bit or 64-bit FP registers. The
1 default value is restored by '.set fp=default'.
1
1 '-modd-spreg'
1 '-mno-odd-spreg'
1 Enable use of floating-point operations on odd-numbered
1 single-precision registers when supported by the ISA. '-mfpxx'
1 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'
1
1 '-mips16'
1 '-no-mips16'
1 Generate code for the MIPS 16 processor. This is equivalent to
1 putting '.module mips16' at the start of the assembly file.
1 '-no-mips16' turns off this option.
1
1 '-mmips16e2'
1 '-mno-mips16e2'
1 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1 equivalent to putting '.module mips16e2' at the start of the
1 assembly file. '-mno-mips16e2' turns off this option.
1
1 '-mmicromips'
1 '-mno-micromips'
1 Generate code for the microMIPS processor. This is equivalent to
1 putting '.module micromips' at the start of the assembly file.
1 '-mno-micromips' turns off this option. This is equivalent to
1 putting '.module nomicromips' at the start of the assembly file.
1
1 '-msmartmips'
1 '-mno-smartmips'
1 Enables the SmartMIPS extensions to the MIPS32 instruction set,
1 which provides a number of new instructions which target smartcard
1 and cryptographic applications. This is equivalent to putting
1 '.module smartmips' at the start of the assembly file.
1 '-mno-smartmips' turns off this option.
1
1 '-mips3d'
1 '-no-mips3d'
1 Generate code for the MIPS-3D Application Specific Extension. This
1 tells the assembler to accept MIPS-3D instructions. '-no-mips3d'
1 turns off this option.
1
1 '-mdmx'
1 '-no-mdmx'
1 Generate code for the MDMX Application Specific Extension. This
1 tells the assembler to accept MDMX instructions. '-no-mdmx' turns
1 off this option.
1
1 '-mdsp'
1 '-mno-dsp'
1 Generate code for the DSP Release 1 Application Specific Extension.
1 This tells the assembler to accept DSP Release 1 instructions.
1 '-mno-dsp' turns off this option.
1
1 '-mdspr2'
1 '-mno-dspr2'
1 Generate code for the DSP Release 2 Application Specific Extension.
1 This option implies '-mdsp'. This tells the assembler to accept
1 DSP Release 2 instructions. '-mno-dspr2' turns off this option.
1
1 '-mdspr3'
1 '-mno-dspr3'
1 Generate code for the DSP Release 3 Application Specific Extension.
1 This option implies '-mdsp' and '-mdspr2'. This tells the
1 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns
1 off this option.
1
1 '-mmt'
1 '-mno-mt'
1 Generate code for the MT Application Specific Extension. This
1 tells the assembler to accept MT instructions. '-mno-mt' turns off
1 this option.
1
1 '-mmcu'
1 '-mno-mcu'
1 Generate code for the MCU Application Specific Extension. This
1 tells the assembler to accept MCU instructions. '-mno-mcu' turns
1 off this option.
1
1 '-mmsa'
1 '-mno-msa'
1 Generate code for the MIPS SIMD Architecture Extension. This tells
1 the assembler to accept MSA instructions. '-mno-msa' turns off
1 this option.
1
1 '-mxpa'
1 '-mno-xpa'
1 Generate code for the MIPS eXtended Physical Address (XPA)
1 Extension. This tells the assembler to accept XPA instructions.
1 '-mno-xpa' turns off this option.
1
1 '-mvirt'
1 '-mno-virt'
1 Generate code for the Virtualization Application Specific
1 Extension. This tells the assembler to accept Virtualization
1 instructions. '-mno-virt' turns off this option.
1
1 '-minsn32'
1 '-mno-insn32'
1 Only use 32-bit instruction encodings when generating code for the
1 microMIPS processor. This option inhibits the use of any 16-bit
1 instructions. This is equivalent to putting '.set insn32' at the
1 start of the assembly file. '-mno-insn32' turns off this option.
1 This is equivalent to putting '.set noinsn32' at the start of the
1 assembly file. By default '-mno-insn32' is selected, allowing all
1 instructions to be used.
1
1 '-mfix7000'
1 '-mno-fix7000'
1 Cause nops to be inserted if the read of the destination register
1 of an mfhi or mflo instruction occurs in the following two
1 instructions.
1
1 '-mfix-rm7000'
1 '-mno-fix-rm7000'
1 Cause nops to be inserted if a dmult or dmultu instruction is
1 followed by a load instruction.
1
1 '-mfix-loongson2f-jump'
1 '-mno-fix-loongson2f-jump'
1 Eliminate instruction fetch from outside 256M region to work around
1 the Loongson2F 'jump' instructions. Without it, under extreme
1 cases, the kernel may crash. The issue has been solved in latest
1 processor batches, but this fix has no side effect to them.
1
1 '-mfix-loongson2f-nop'
1 '-mno-fix-loongson2f-nop'
1 Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop'
1 errata. Without it, under extreme cases, the CPU might deadlock.
1 The issue has been solved in later Loongson2F batches, but this fix
1 has no side effect to them.
1
1 '-mfix-vr4120'
1 '-mno-fix-vr4120'
1 Insert nops to work around certain VR4120 errata. This option is
1 intended to be used on GCC-generated code: it is not designed to
1 catch all problems in hand-written assembler code.
1
1 '-mfix-vr4130'
1 '-mno-fix-vr4130'
1 Insert nops to work around the VR4130 'mflo'/'mfhi' errata.
1
1 '-mfix-24k'
1 '-mno-fix-24k'
1 Insert nops to work around the 24K 'eret'/'deret' errata.
1
1 '-mfix-cn63xxp1'
1 '-mno-fix-cn63xxp1'
1 Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around
1 certain CN63XXP1 errata.
1
1 '-m4010'
1 '-no-m4010'
1 Generate code for the LSI R4010 chip. This tells the assembler to
1 accept the R4010-specific instructions ('addciu', 'ffc', etc.), and
1 to not schedule 'nop' instructions around accesses to the 'HI' and
1 'LO' registers. '-no-m4010' turns off this option.
1
1 '-m4650'
1 '-no-m4650'
1 Generate code for the MIPS R4650 chip. This tells the assembler to
1 accept the 'mad' and 'madu' instruction, and to not schedule 'nop'
1 instructions around accesses to the 'HI' and 'LO' registers.
1 '-no-m4650' turns off this option.
1
1 '-m3900'
1 '-no-m3900'
1 '-m4100'
1 '-no-m4100'
1 For each option '-mNNNN', generate code for the MIPS RNNNN chip.
1 This tells the assembler to accept instructions specific to that
1 chip, and to schedule for that chip's hazards.
1
1 '-march=CPU'
1 Generate code for a particular MIPS CPU. It is exactly equivalent
1 to '-mCPU', except that there are more value of CPU understood.
1 Valid CPU value are:
1
1 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
1 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
1 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
1 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
1 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc,
1 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1,
1 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf,
1 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1,
1 interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf,
1 20kc, 25kf, sb1, sb1a, i6400, p6600, loongson2e, loongson2f,
1 loongson3a, octeon, octeon+, octeon2, octeon3, xlr, xlp
1
1 For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms
1 for 'Nf1_1'. These values are deprecated.
1
1 '-mtune=CPU'
1 Schedule and tune for a particular MIPS CPU. Valid CPU values are
1 identical to '-march=CPU'.
1
1 '-mabi=ABI'
1 Record which ABI the source code uses. The recognized arguments
1 are: '32', 'n32', 'o64', '64' and 'eabi'.
1
1 '-msym32'
1 '-mno-sym32'
1 Equivalent to adding '.set sym32' or '.set nosym32' to the
1 beginning of the assembler input. ⇒MIPS Symbol Sizes.
1
1 '-nocpp'
1 This option is ignored. It is accepted for command-line
1 compatibility with other assemblers, which use it to turn off C
1 style preprocessing. With GNU 'as', there is no need for '-nocpp',
1 because the GNU assembler itself never runs the C preprocessor.
1
1 '-msoft-float'
1 '-mhard-float'
1 Disable or enable floating-point instructions. Note that by
1 default floating-point instructions are always allowed even with
1 CPU targets that don't have support for these instructions.
1
1 '-msingle-float'
1 '-mdouble-float'
1 Disable or enable double-precision floating-point operations. Note
1 that by default double-precision floating-point operations are
1 always allowed even with CPU targets that don't have support for
1 these operations.
1
1 '--construct-floats'
1 '--no-construct-floats'
1 The '--no-construct-floats' option disables the construction of
1 double width floating point constants by loading the two halves of
1 the value into the two single width floating point registers that
1 make up the double width register. This feature is useful if the
1 processor support the FR bit in its status register, and this bit
1 is known (by the programmer) to be set. This bit prevents the
1 aliasing of the double width register by the single width
1 registers.
1
1 By default '--construct-floats' is selected, allowing construction
1 of these floating point constants.
1
1 '--relax-branch'
1 '--no-relax-branch'
1 The '--relax-branch' option enables the relaxation of out-of-range
1 branches. Any branches whose target cannot be reached directly are
1 converted to a small instruction sequence including an
1 inverse-condition branch to the physically next instruction, and a
1 jump to the original target is inserted between the two
1 instructions. In PIC code the jump will involve further
1 instructions for address calculation.
1
1 The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and
1 'BPOSGE64' instructions are excluded from relaxation, because they
1 have no complementing counterparts. They could be relaxed with the
1 use of a longer sequence involving another branch, however this has
1 not been implemented and if their target turns out of reach, they
1 produce an error even if branch relaxation is enabled.
1
1 Also no MIPS16 branches are ever relaxed.
1
1 By default '--no-relax-branch' is selected, causing any
1 out-of-range branches to produce an error.
1
1 '-mignore-branch-isa'
1 '-mno-ignore-branch-isa'
1 Ignore branch checks for invalid transitions between ISA modes.
1
1 The semantics of branches does not provide for an ISA mode switch,
1 so in most cases the ISA mode a branch has been encoded for has to
1 be the same as the ISA mode of the branch's target label. If the
1 ISA modes do not match, then such a branch, if taken, will cause
1 the ISA mode to remain unchanged and instructions that follow will
1 be executed in the wrong ISA mode causing the program to misbehave
1 or crash.
1
1 In the case of the 'BAL' instruction it may be possible to relax it
1 to an equivalent 'JALX' instruction so that the ISA mode is
1 switched at the run time as required. For other branches no
1 relaxation is possible and therefore GAS has checks implemented
1 that verify in branch assembly that the two ISA modes match, and
1 report an error otherwise so that the problem with code can be
1 diagnosed at the assembly time rather than at the run time.
1
1 However some assembly code, including generated code produced by
1 some versions of GCC, may incorrectly include branches to data
1 labels, which appear to require a mode switch but are either dead
1 or immediately followed by valid instructions encoded for the same
1 ISA the branch has been encoded for. While not strictly correct at
1 the source level such code will execute as intended, so to help
1 with these cases '-mignore-branch-isa' is supported which disables
1 ISA mode checks for branches.
1
1 By default '-mno-ignore-branch-isa' is selected, causing any
1 invalid branch requiring a transition between ISA modes to produce
1 an error.
1
1 '-mnan=ENCODING'
1 This option indicates whether the source code uses the IEEE 2008
1 NaN encoding ('-mnan=2008') or the original MIPS encoding
1 ('-mnan=legacy'). It is equivalent to adding a '.nan' directive to
1 the beginning of the source file. ⇒MIPS NaN Encodings.
1
1 '-mnan=legacy' is the default if no '-mnan' option or '.nan'
1 directive is used.
1
1 '--trap'
1 '--no-break'
1 'as' automatically macro expands certain division and
1 multiplication instructions to check for overflow and division by
1 zero. This option causes 'as' to generate code to take a trap
1 exception rather than a break exception when an error is detected.
1 The trap instructions are only supported at Instruction Set
1 Architecture level 2 and higher.
1
1 '--break'
1 '--no-trap'
1 Generate code to take a break exception rather than a trap
1 exception when an error is detected. This is the default.
1
1 '-mpdr'
1 '-mno-pdr'
1 Control generation of '.pdr' sections. Off by default on IRIX, on
1 elsewhere.
1
1 '-mshared'
1 '-mno-shared'
1 When generating code using the Unix calling conventions (selected
1 by '-KPIC' or '-mcall_shared'), gas will normally generate code
1 which can go into a shared library. The '-mno-shared' option tells
1 gas to generate code which uses the calling convention, but can not
1 go into a shared library. The resulting code is slightly more
1 efficient. This option only affects the handling of the '.cpload'
1 and '.cpsetup' pseudo-ops.
1