as: MIPS FP ABI Variants

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1 9.27.9.2 Supported FP ABIs
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1 The supported floating-point ABI variants are:
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1 '0 - No floating-point'
1      This variant is used to indicate that floating-point is not used
1      within the module at all and therefore has no impact on the ABI.
1      This is the default.
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1 '1 - Double-precision'
1      This variant indicates that double-precision support is used.  For
1      64-bit ABIs this means that 64-bit wide floating-point registers
1      are required.  For 32-bit ABIs this means that 32-bit wide
1      floating-point registers are required and double-precision
1      operations use pairs of registers.
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1 '2 - Single-precision'
1      This variant indicates that single-precision support is used.
1      Double precision operations will be supported via soft-float
1      routines.
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1 '3 - Soft-float'
1      This variant indicates that although floating-point support is used
1      all operations are emulated in software.  This means the ABI is
1      modified to pass all floating-point data in general-purpose
1      registers.
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1 '4 - Deprecated'
1      This variant existed as an initial attempt at supporting 64-bit
1      wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This
1      has been superseded by 5, 6 and 7.
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1 '5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU'
1      This variant is used by 32-bit ABIs to indicate that the
1      floating-point code in the module has been designed to operate
1      correctly with either 32-bit wide or 64-bit wide floating-point
1      registers.  Double-precision support is used.  Only O32 currently
1      supports this variant and requires a minimum architecture of MIPS
1      II.
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1 '6 - Double-precision 32-bit FPU, 64-bit FPU'
1      This variant is used by 32-bit ABIs to indicate that the
1      floating-point code in the module requires 64-bit wide
1      floating-point registers.  Double-precision support is used.  Only
1      O32 currently supports this variant and requires a minimum
1      architecture of MIPS32r2.
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1 '7 - Double-precision compat 32-bit FPU, 64-bit FPU'
1      This variant is used by 32-bit ABIs to indicate that the
1      floating-point code in the module requires 64-bit wide
1      floating-point registers.  Double-precision support is used.  This
1      differs from the previous ABI as it restricts use of odd-numbered
1      single-precision registers.  Only O32 currently supports this
1      variant and requires a minimum architecture of MIPS32r2.
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