as: M68HC11-Branch
1
1 9.24.6.1 Branch Improvement
1 ...........................
1
1 Certain pseudo opcodes are permitted for branch instructions. They
1 expand to the shortest branch instruction that reach the target.
1 Generally these mnemonics are made by prepending 'j' to the start of
1 Motorola mnemonic. These pseudo opcodes are not affected by the
1 '--short-branches' or '--force-long-branches' options.
1
1 The following table summarizes the pseudo-operations.
1
1 Displacement Width
1 +-------------------------------------------------------------+
1 | Options |
1 | --short-branches --force-long-branches |
1 +--------------------------+----------------------------------+
1 Op |BYTE WORD | BYTE WORD |
1 +--------------------------+----------------------------------+
1 bsr | bsr <pc-rel> <error> | jsr <abs> |
1 bra | bra <pc-rel> <error> | jmp <abs> |
1 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
1 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
1 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
1 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
1 | jmp <abs> | |
1 +--------------------------+----------------------------------+
1 XX: condition
1 NX: negative of condition XX
1
1
1 'jbsr'
1 'jbra'
1 These are the simplest jump pseudo-operations; they always map to
1 one particular machine instruction, depending on the displacement
1 to the branch target.
1
1 'jbXX'
1 Here, 'jbXX' stands for an entire family of pseudo-operations,
1 where XX is a conditional branch or condition-code test. The full
1 list of pseudo-ops in this family is:
1 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
1 jbcs jbne jblt jble jbls jbvc jbmi
1
1 For the cases of non-PC relative displacements and long
1 displacements, 'as' issues a longer code fragment in terms of NX,
1 the opposite condition to XX. For example, for the non-PC relative
1 case:
1 jbXX foo
1 gives
1 bNXs oof
1 jmp foo
1 oof:
1