as: H8/300 Opcodes
1
1 9.12.5 Opcodes
1 --------------
1
1 For detailed information on the H8/300 machine instruction set, see
1 'H8/300 Series Programming Manual'. For information specific to the
1 H8/300H, see 'H8/300H Series Programming Manual' (Renesas).
1
1 'as' implements all the standard H8/300 opcodes. No additional
1 pseudo-instructions are needed on this family.
1
1 The following table summarizes the H8/300 opcodes, and their
1 arguments. Entries marked '*' are opcodes used only on the H8/300H.
1
1 Legend:
1 Rs source register
1 Rd destination register
1 abs absolute address
1 imm immediate data
1 disp:N N-bit displacement from a register
1 pcrel:N N-bit displacement relative to program counter
1
1 add.b #imm,rd * andc #imm,ccr
1 add.b rs,rd band #imm,rd
1 add.w rs,rd band #imm,@rd
1 * add.w #imm,rd band #imm,@abs:8
1 * add.l rs,rd bra pcrel:8
1 * add.l #imm,rd * bra pcrel:16
1 adds #imm,rd bt pcrel:8
1 addx #imm,rd * bt pcrel:16
1 addx rs,rd brn pcrel:8
1 and.b #imm,rd * brn pcrel:16
1 and.b rs,rd bf pcrel:8
1 * and.w rs,rd * bf pcrel:16
1 * and.w #imm,rd bhi pcrel:8
1 * and.l #imm,rd * bhi pcrel:16
1 * and.l rs,rd bls pcrel:8
1 * bls pcrel:16 bld #imm,rd
1 bcc pcrel:8 bld #imm,@rd
1 * bcc pcrel:16 bld #imm,@abs:8
1 bhs pcrel:8 bnot #imm,rd
1 * bhs pcrel:16 bnot #imm,@rd
1 bcs pcrel:8 bnot #imm,@abs:8
1 * bcs pcrel:16 bnot rs,rd
1 blo pcrel:8 bnot rs,@rd
1 * blo pcrel:16 bnot rs,@abs:8
1 bne pcrel:8 bor #imm,rd
1 * bne pcrel:16 bor #imm,@rd
1 beq pcrel:8 bor #imm,@abs:8
1 * beq pcrel:16 bset #imm,rd
1 bvc pcrel:8 bset #imm,@rd
1 * bvc pcrel:16 bset #imm,@abs:8
1 bvs pcrel:8 bset rs,rd
1 * bvs pcrel:16 bset rs,@rd
1 bpl pcrel:8 bset rs,@abs:8
1 * bpl pcrel:16 bsr pcrel:8
1 bmi pcrel:8 bsr pcrel:16
1 * bmi pcrel:16 bst #imm,rd
1 bge pcrel:8 bst #imm,@rd
1 * bge pcrel:16 bst #imm,@abs:8
1 blt pcrel:8 btst #imm,rd
1 * blt pcrel:16 btst #imm,@rd
1 bgt pcrel:8 btst #imm,@abs:8
1 * bgt pcrel:16 btst rs,rd
1 ble pcrel:8 btst rs,@rd
1 * ble pcrel:16 btst rs,@abs:8
1 bclr #imm,rd bxor #imm,rd
1 bclr #imm,@rd bxor #imm,@rd
1 bclr #imm,@abs:8 bxor #imm,@abs:8
1 bclr rs,rd cmp.b #imm,rd
1 bclr rs,@rd cmp.b rs,rd
1 bclr rs,@abs:8 cmp.w rs,rd
1 biand #imm,rd cmp.w rs,rd
1 biand #imm,@rd * cmp.w #imm,rd
1 biand #imm,@abs:8 * cmp.l #imm,rd
1 bild #imm,rd * cmp.l rs,rd
1 bild #imm,@rd daa rs
1 bild #imm,@abs:8 das rs
1 bior #imm,rd dec.b rs
1 bior #imm,@rd * dec.w #imm,rd
1 bior #imm,@abs:8 * dec.l #imm,rd
1 bist #imm,rd divxu.b rs,rd
1 bist #imm,@rd * divxu.w rs,rd
1 bist #imm,@abs:8 * divxs.b rs,rd
1 bixor #imm,rd * divxs.w rs,rd
1 bixor #imm,@rd eepmov
1 bixor #imm,@abs:8 * eepmovw
1 * exts.w rd mov.w rs,@abs:16
1 * exts.l rd * mov.l #imm,rd
1 * extu.w rd * mov.l rs,rd
1 * extu.l rd * mov.l @rs,rd
1 inc rs * mov.l @(disp:16,rs),rd
1 * inc.w #imm,rd * mov.l @(disp:24,rs),rd
1 * inc.l #imm,rd * mov.l @rs+,rd
1 jmp @rs * mov.l @abs:16,rd
1 jmp abs * mov.l @abs:24,rd
1 jmp @@abs:8 * mov.l rs,@rd
1 jsr @rs * mov.l rs,@(disp:16,rd)
1 jsr abs * mov.l rs,@(disp:24,rd)
1 jsr @@abs:8 * mov.l rs,@-rd
1 ldc #imm,ccr * mov.l rs,@abs:16
1 ldc rs,ccr * mov.l rs,@abs:24
1 * ldc @abs:16,ccr movfpe @abs:16,rd
1 * ldc @abs:24,ccr movtpe rs,@abs:16
1 * ldc @(disp:16,rs),ccr mulxu.b rs,rd
1 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd
1 * ldc @rs+,ccr * mulxs.b rs,rd
1 * ldc @rs,ccr * mulxs.w rs,rd
1 * mov.b @(disp:24,rs),rd neg.b rs
1 * mov.b rs,@(disp:24,rd) * neg.w rs
1 mov.b @abs:16,rd * neg.l rs
1 mov.b rs,rd nop
1 mov.b @abs:8,rd not.b rs
1 mov.b rs,@abs:8 * not.w rs
1 mov.b rs,rd * not.l rs
1 mov.b #imm,rd or.b #imm,rd
1 mov.b @rs,rd or.b rs,rd
1 mov.b @(disp:16,rs),rd * or.w #imm,rd
1 mov.b @rs+,rd * or.w rs,rd
1 mov.b @abs:8,rd * or.l #imm,rd
1 mov.b rs,@rd * or.l rs,rd
1 mov.b rs,@(disp:16,rd) orc #imm,ccr
1 mov.b rs,@-rd pop.w rs
1 mov.b rs,@abs:8 * pop.l rs
1 mov.w rs,@rd push.w rs
1 * mov.w @(disp:24,rs),rd * push.l rs
1 * mov.w rs,@(disp:24,rd) rotl.b rs
1 * mov.w @abs:24,rd * rotl.w rs
1 * mov.w rs,@abs:24 * rotl.l rs
1 mov.w rs,rd rotr.b rs
1 mov.w #imm,rd * rotr.w rs
1 mov.w @rs,rd * rotr.l rs
1 mov.w @(disp:16,rs),rd rotxl.b rs
1 mov.w @rs+,rd * rotxl.w rs
1 mov.w @abs:16,rd * rotxl.l rs
1 mov.w rs,@(disp:16,rd) rotxr.b rs
1 mov.w rs,@-rd * rotxr.w rs
1 * rotxr.l rs * stc ccr,@(disp:24,rd)
1 bpt * stc ccr,@-rd
1 rte * stc ccr,@abs:16
1 rts * stc ccr,@abs:24
1 shal.b rs sub.b rs,rd
1 * shal.w rs sub.w rs,rd
1 * shal.l rs * sub.w #imm,rd
1 shar.b rs * sub.l rs,rd
1 * shar.w rs * sub.l #imm,rd
1 * shar.l rs subs #imm,rd
1 shll.b rs subx #imm,rd
1 * shll.w rs subx rs,rd
1 * shll.l rs * trapa #imm
1 shlr.b rs xor #imm,rd
1 * shlr.w rs xor rs,rd
1 * shlr.l rs * xor.w #imm,rd
1 sleep * xor.w rs,rd
1 stc ccr,rd * xor.l #imm,rd
1 * stc ccr,@rs * xor.l rs,rd
1 * stc ccr,@(disp:16,rd) xorc #imm,ccr
1
1 Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined
1 with variants using the suffixes '.b', '.w', and '.l' to specify the
1 size of a memory operand. 'as' supports these suffixes, but does not
1 require them; since one of the operands is always a register, 'as' can
1 deduce the correct size.
1
1 For example, since 'r0' refers to a 16-bit register,
1 mov r0,@foo
1 is equivalent to
1 mov.w r0,@foo
1
1 If you use the size suffixes, 'as' issues a warning when the suffix
1 and the register size do not match.
1