as: Blackfin Syntax
1
1 9.6.2 Syntax
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1
1 'Special Characters'
1 Assembler input is free format and may appear anywhere on the line.
1 One instruction may extend across multiple lines or more than one
1 instruction may appear on the same line. White space (space, tab,
1 comments or newline) may appear anywhere between tokens. A token
1 must not have embedded spaces. Tokens include numbers, register
1 names, keywords, user identifiers, and also some multicharacter
1 special symbols like "+=", "/*" or "||".
1
1 Comments are introduced by the '#' character and extend to the end
1 of the current line. If the '#' appears as the first character of
1 a line, the whole line is treated as a comment, but in this case
11 Comments::) or a preprocessor control command (⇒
Preprocessing).
1
1 'Instruction Delimiting'
1 A semicolon must terminate every instruction. Sometimes a complete
1 instruction will consist of more than one operation. There are two
1 cases where this occurs. The first is when two general operations
1 are combined. Normally a comma separates the different parts, as
1 in
1
1 a0= r3.h * r2.l, a1 = r3.l * r2.h ;
1
1 The second case occurs when a general instruction is combined with
1 one or two memory references for joint issue. The latter portions
1 are set off by a "||" token.
1
1 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
1
1 Multiple instructions can occur on the same line. Each must be
1 terminated by a semicolon character.
1
1 'Register Names'
1
1 The assembler treats register names and instruction keywords in a
1 case insensitive manner. User identifiers are case sensitive.
1 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
1 assembler.
1
1 Register names are reserved and may not be used as program
1 identifiers.
1
1 Some operations (such as "Move Register") require a register pair.
1 Register pairs are always data registers and are denoted using a
1 colon, eg., R3:2. The larger number must be written firsts. Note
1 that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
1 R3:2, and R1:0.
1
1 Some instructions (such as -SP (Push Multiple)) require a group of
1 adjacent registers. Adjacent registers are denoted in the syntax
1 by the range enclosed in parentheses and separated by a colon, eg.,
1 (R7:3). Again, the larger number appears first.
1
1 Portions of a particular register may be individually specified.
1 This is written with a dot (".") following the register name and
1 then a letter denoting the desired portion. For 32-bit registers,
1 ".H" denotes the most significant ("High") portion. ".L" denotes
1 the least-significant portion. The subdivisions of the 40-bit
1 registers are described later.
1
1 'Accumulators'
1 The set of 40-bit registers A1 and A0 that normally contain data
1 that is being manipulated. Each accumulator can be accessed in
1 four ways.
1
1 'one 40-bit register'
1 The register will be referred to as A1 or A0.
1 'one 32-bit register'
1 The registers are designated as A1.W or A0.W.
1 'two 16-bit registers'
1 The registers are designated as A1.H, A1.L, A0.H or A0.L.
1 'one 8-bit register'
1 The registers are designated as A1.X or A0.X for the bits that
1 extend beyond bit 31.
1
1 'Data Registers'
1 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
1 that normally contain data for manipulation. These are abbreviated
1 as D-register or Dreg. Data registers can be accessed as 32-bit
1 registers or as two independent 16-bit registers. The least
1 significant 16 bits of each register is called the "low" half and
1 is designated with ".L" following the register name. The most
1 significant 16 bits are called the "high" half and is designated
1 with ".H" following the name.
1
1 R7.L, r2.h, r4.L, R0.H
1
1 'Pointer Registers'
1 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
1 that normally contain byte addresses of data structures. These are
1 abbreviated as P-register or Preg.
1
1 p2, p5, fp, sp
1
1 'Stack Pointer SP'
1 The stack pointer contains the 32-bit address of the last occupied
1 byte location in the stack. The stack grows by decrementing the
1 stack pointer.
1
1 'Frame Pointer FP'
1 The frame pointer contains the 32-bit address of the previous frame
1 pointer in the stack. It is located at the top of a frame.
1
1 'Loop Top'
1 LT0 and LT1. These registers contain the 32-bit address of the top
1 of a zero overhead loop.
1
1 'Loop Count'
1 LC0 and LC1. These registers contain the 32-bit counter of the
1 zero overhead loop executions.
1
1 'Loop Bottom'
1 LB0 and LB1. These registers contain the 32-bit address of the
1 bottom of a zero overhead loop.
1
1 'Index Registers'
1 The set of 32-bit registers (I0, I1, I2, I3) that normally contain
1 byte addresses of data structures. Abbreviated I-register or Ireg.
1
1 'Modify Registers'
1 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
1 offset values that are added and subtracted to one of the index
1 registers. Abbreviated as Mreg.
1
1 'Length Registers'
1 The set of 32-bit registers (L0, L1, L2, L3) that normally contain
1 the length in bytes of the circular buffer. Abbreviated as Lreg.
1 Clear the Lreg to disable circular addressing for the corresponding
1 Ireg.
1
1 'Base Registers'
1 The set of 32-bit registers (B0, B1, B2, B3) that normally contain
1 the base address in bytes of the circular buffer. Abbreviated as
1 Breg.
1
1 'Floating Point'
1 The Blackfin family has no hardware floating point but the .float
1 directive generates ieee floating point numbers for use with
1 software floating point libraries.
1
1 'Blackfin Opcodes'
1 For detailed information on the Blackfin machine instruction set,
1 see the Blackfin(r) Processor Instruction Set Reference.
1