as: ARM Options
1
1 9.4.1 Options
1 -------------
1
1 '-mcpu=PROCESSOR[+EXTENSION...]'
1 This option specifies the target processor. The assembler will
1 issue an error message if an attempt is made to assemble an
1 instruction which will not execute on the target processor. The
1 following processor names are recognized: 'arm1', 'arm2', 'arm250',
1 'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7',
1 'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700',
1 'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t',
1 'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi',
1 'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1',
1 'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920',
1 'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526
1 processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e',
1 'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0',
1 'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi',
1 'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e',
1 'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te'
1 (Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor),
1 'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE
1 processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s',
1 'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore',
1 'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9',
1 'cortex-a15', 'cortex-a17', 'cortex-a32', 'cortex-a35',
1 'cortex-a53', 'cortex-a55', 'cortex-a57', 'cortex-a72',
1 'cortex-a73', 'cortex-a75', 'cortex-r4', 'cortex-r4f', 'cortex-r5',
1 'cortex-r7', 'cortex-r8', 'cortex-r52', 'cortex-m33', 'cortex-m23',
1 'cortex-m7', 'cortex-m4', 'cortex-m3', 'cortex-m1', 'cortex-m0',
1 'cortex-m0plus', 'exynos-m1', 'marvell-pj4', 'marvell-whitney',
1 'xgene1', 'xgene2', 'ep9312' (ARM920 with Cirrus Maverick
1 coprocessor), 'i80200' (Intel XScale processor) 'iwmmxt' (Intel(r)
1 XScale processor with Wireless MMX(tm) technology coprocessor) and
1 'xscale'. The special name 'all' may be used to allow the
1 assembler to accept instructions valid for any ARM processor.
1
1 In addition to the basic instruction set, the assembler can be told
1 to accept various extension mnemonics that extend the processor
1 using the co-processor instruction space. For example,
1 '-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'.
1
1 Multiple extensions may be specified, separated by a '+'. The
1 extensions should be specified in ascending alphabetical order.
1
1 Some extensions may be restricted to particular architectures; this
1 is documented in the list of extensions below.
1
1 Extension mnemonics may also be removed from those the assembler
1 accepts. This is done be prepending 'no' to the option that adds
1 the extension. Extensions that are removed should be listed after
1 all extensions which have been added, again in ascending
1 alphabetical order. For example, '-mcpu=ep9312+nomaverick' is
1 equivalent to specifying '-mcpu=arm920'.
1
1 The following extensions are currently supported: 'crc' 'crypto'
1 (Cryptography Extensions for v8-A architecture, implies 'fp+simd'),
1 'dotprod' (Dot Product Extensions for v8.2-A architecture, implies
1 'fp+simd'), 'fp' (Floating Point Extensions for v8-A architecture),
1 'fp16' (FP16 Extensions for v8.2-A architecture, implies 'fp'),
1 'fp16fml' (FP16 Floating Point Multiplication Variant Extensions
1 for v8.2-A architecture, implies 'fp16'), 'idiv' (Integer Divide
1 Extensions for v7-A and v7-R architectures), 'iwmmxt', 'iwmmxt2',
1 'xscale', 'maverick', 'mp' (Multiprocessing Extensions for v7-A and
1 v7-R architectures), 'os' (Operating System for v6M architecture),
1 'sec' (Security Extensions for v6K and v7-A architectures), 'simd'
1 (Advanced SIMD Extensions for v8-A architecture, implies 'fp'),
1 'virt' (Virtualization Extensions for v7-A architecture, implies
1 'idiv'), 'pan' (Privileged Access Never Extensions for v8-A
1 architecture), 'ras' (Reliability, Availability and Serviceability
1 extensions for v8-A architecture), 'rdma' (ARMv8.1 Advanced SIMD
1 extensions for v8-A architecture, implies 'simd') and 'xscale'.
1
1 '-march=ARCHITECTURE[+EXTENSION...]'
1 This option specifies the target architecture. The assembler will
1 issue an error message if an attempt is made to assemble an
1 instruction which will not execute on the target architecture. The
1 following architecture names are recognized: 'armv1', 'armv2',
1 'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm',
1 'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te',
1 'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6kz',
1 'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r',
1 'armv7-m', 'armv7e-m', 'armv8-a', 'armv8.1-a', 'armv8.2-a',
1 'armv8.3-a', 'armv8-r', 'armv8.4-a', 'iwmmxt' 'iwmmxt2' and
1 'xscale'. If both '-mcpu' and '-march' are specified, the
1 assembler will use the setting for '-mcpu'.
1
1 The architecture option can be extended with the same instruction
1 set extension options as the '-mcpu' option.
1
1 '-mfpu=FLOATING-POINT-FORMAT'
1
1 This option specifies the floating point format to assemble for.
1 The assembler will issue an error message if an attempt is made to
1 assemble an instruction which will not execute on the target
1 floating point unit. The following format options are recognized:
1 'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11',
1 'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0',
1 'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16',
1 'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16',
1 'fpv4-sp-d16', 'fpv5-sp-d16', 'fpv5-d16', 'fp-armv8', 'arm1020t',
1 'arm1020e', 'arm1136jf-s', 'maverick', 'neon', 'neon-vfpv3',
1 'neon-fp16', 'neon-vfpv4', 'neon-fp-armv8', 'crypto-neon-fp-armv8',
1 'neon-fp-armv8.1' and 'crypto-neon-fp-armv8.1'.
1
1 In addition to determining which instructions are assembled, this
1 option also affects the way in which the '.double' assembler
1 directive behaves when assembling little-endian code.
1
1 The default is dependent on the processor selected. For
1 Architecture 5 or later, the default is to assemble for VFP
1 instructions; for earlier architectures the default is to assemble
1 for FPA instructions.
1
1 '-mthumb'
1 This option specifies that the assembler should start assembling
1 Thumb instructions; that is, it should behave as though the file
1 starts with a '.code 16' directive.
1
1 '-mthumb-interwork'
1 This option specifies that the output generated by the assembler
1 should be marked as supporting interworking.
1
1 '-mimplicit-it=never'
1 '-mimplicit-it=always'
1 '-mimplicit-it=arm'
1 '-mimplicit-it=thumb'
1 The '-mimplicit-it' option controls the behavior of the assembler
1 when conditional instructions are not enclosed in IT blocks. There
1 are four possible behaviors. If 'never' is specified, such
1 constructs cause a warning in ARM code and an error in Thumb-2
1 code. If 'always' is specified, such constructs are accepted in
1 both ARM and Thumb-2 code, where the IT instruction is added
1 implicitly. If 'arm' is specified, such constructs are accepted in
1 ARM code and cause an error in Thumb-2 code. If 'thumb' is
1 specified, such constructs cause a warning in ARM code and are
1 accepted in Thumb-2 code. If you omit this option, the behavior is
1 equivalent to '-mimplicit-it=arm'.
1
1 '-mapcs-26'
1 '-mapcs-32'
1 These options specify that the output generated by the assembler
1 should be marked as supporting the indicated version of the Arm
1 Procedure. Calling Standard.
1
1 '-matpcs'
1 This option specifies that the output generated by the assembler
1 should be marked as supporting the Arm/Thumb Procedure Calling
1 Standard. If enabled this option will cause the assembler to
1 create an empty debugging section in the object file called
1 .arm.atpcs. Debuggers can use this to determine the ABI being used
1 by.
1
1 '-mapcs-float'
1 This indicates the floating point variant of the APCS should be
1 used. In this variant floating point arguments are passed in FP
1 registers rather than integer registers.
1
1 '-mapcs-reentrant'
1 This indicates that the reentrant variant of the APCS should be
1 used. This variant supports position independent code.
1
1 '-mfloat-abi=ABI'
1 This option specifies that the output generated by the assembler
1 should be marked as using specified floating point ABI. The
1 following values are recognized: 'soft', 'softfp' and 'hard'.
1
1 '-meabi=VER'
1 This option specifies which EABI version the produced object files
1 should conform to. The following values are recognized: 'gnu', '4'
1 and '5'.
1
1 '-EB'
1 This option specifies that the output generated by the assembler
1 should be marked as being encoded for a big-endian processor.
1
1 Note: If a program is being built for a system with big-endian data
1 and little-endian instructions then it should be assembled with the
1 '-EB' option, (all of it, code and data) and then linked with the
1 '--be8' option. This will reverse the endianness of the
1 instructions back to little-endian, but leave the data as
1 big-endian.
1
1 '-EL'
1 This option specifies that the output generated by the assembler
1 should be marked as being encoded for a little-endian processor.
1
1 '-k'
1 This option specifies that the output of the assembler should be
1 marked as position-independent code (PIC).
1
1 '--fix-v4bx'
1 Allow 'BX' instructions in ARMv4 code. This is intended for use
1 with the linker option of the same name.
1
1 '-mwarn-deprecated'
1 '-mno-warn-deprecated'
1 Enable or disable warnings about using deprecated options or
1 features. The default is to warn.
1
1 '-mccs'
1 Turns on CodeComposer Studio assembly syntax compatibility mode.
1
1 '-mwarn-syms'
1 '-mno-warn-syms'
1 Enable or disable warnings about symbols that match the names of
1 ARM instructions. The default is to warn.
1