as: ARC Directives
1
1 9.3.3 ARC Machine Directives
1 ----------------------------
1
1 The ARC version of 'as' supports the following additional machine
1 directives:
1
1 '.lcomm SYMBOL, LENGTH[, ALIGNMENT]'
1 Reserve LENGTH (an absolute expression) bytes for a local common
1 denoted by SYMBOL. The section and value of SYMBOL are those of
1 the new local common. The addresses are allocated in the bss
1 section, so that at run-time the bytes start off zeroed. Since
1 SYMBOL is not declared global, it is normally not visible to 'ld'.
1 The optional third parameter, ALIGNMENT, specifies the desired
1 alignment of the symbol in the bss section, specified as a byte
1 boundary (for example, an alignment of 16 means that the least
1 significant 4 bits of the address should be zero). The alignment
1 must be an absolute expression, and it must be a power of two. If
1 no alignment is specified, as will set the alignment to the largest
1 power of two less than or equal to the size of the symbol, up to a
1 maximum of 16.
1
1 '.lcommon SYMBOL, LENGTH[, ALIGNMENT]'
1 The same as 'lcomm' directive.
1
1 '.cpu CPU'
1 The '.cpu' directive must be followed by the desired core version.
1 Permitted values for CPU are:
1 'ARC600'
1 Assemble for the ARC600 instruction set.
1
1 'arc600_norm'
1 Assemble for ARC 600 with norm instructions.
1
1 'arc600_mul64'
1 Assemble for ARC 600 with mul64 instructions.
1
1 'arc600_mul32x16'
1 Assemble for ARC 600 with mul32x16 instructions.
1
1 'arc601'
1 Assemble for ARC 601 instruction set.
1
1 'arc601_norm'
1 Assemble for ARC 601 with norm instructions.
1
1 'arc601_mul64'
1 Assemble for ARC 601 with mul64 instructions.
1
1 'arc601_mul32x16'
1 Assemble for ARC 601 with mul32x16 instructions.
1
1 'ARC700'
1 Assemble for the ARC700 instruction set.
1
1 'NPS400'
1 Assemble for the NPS400 instruction set.
1
1 'EM'
1 Assemble for the ARC EM instruction set.
1
1 'arcem'
1 Assemble for ARC EM instruction set
1
1 'em4'
1 Assemble for ARC EM with code-density instructions.
1
1 'em4_dmips'
1 Assemble for ARC EM with code-density instructions.
1
1 'em4_fpus'
1 Assemble for ARC EM with code-density instructions.
1
1 'em4_fpuda'
1 Assemble for ARC EM with code-density, and double-precision
1 assist instructions.
1
1 'quarkse_em'
1 Assemble for QuarkSE-EM instruction set.
1
1 'HS'
1 Assemble for the ARC HS instruction set.
1
1 'archs'
1 Assemble for ARC HS instruction set.
1
1 'hs'
1 Assemble for ARC HS instruction set.
1
1 'hs34'
1 Assemble for ARC HS34 instruction set.
1
1 'hs38'
1 Assemble for ARC HS38 instruction set.
1
1 'hs38_linux'
1 Assemble for ARC HS38 with floating point support on.
1
1 Note: the '.cpu' directive overrides the command line option
1 '-mcpu=CPU'; a warning is emitted when the version is not
1 consistent between the two.
1
1 '.extAuxRegister NAME, ADDR, MODE'
1 Auxiliary registers can be defined in the assembler source code by
1 using this directive. The first parameter, NAME, is the name of
1 the new auxiliary register. The second parameter, ADDR, is address
1 the of the auxiliary register. The third parameter, MODE,
1 specifies whether the register is readable and/or writable and is
1 one of:
1 'r'
1 Read only;
1
1 'w'
1 Write only;
1
1 'r|w'
1 Read and write.
1
1 For example:
1 .extAuxRegister mulhi, 0x12, w
1 specifies a write only extension auxiliary register, MULHI at
1 address 0x12.
1
1 '.extCondCode SUFFIX, VAL'
1 ARC supports extensible condition codes. This directive defines a
1 new condition code, to be known by the suffix, SUFFIX and will
1 depend on the value, VAL in the condition code.
1
1 For example:
1 .extCondCode is_busy,0x14
1 add.is_busy r1,r2,r3
1 will only execute the 'add' instruction if the condition code value
1 is 0x14.
1
1 '.extCoreRegister NAME, REGNUM, MODE, SHORTCUT'
1 Specifies an extension core register named NAME as a synonym for
1 the register numbered REGNUM. The register number must be between
1 32 and 59. The third argument, MODE, indicates whether the
1 register is readable and/or writable and is one of:
1 'r'
1 Read only;
1
1 'w'
1 Write only;
1
1 'r|w'
1 Read and write.
1
1 The final parameter, SHORTCUT indicates whether the register has a
1 short cut in the pipeline. The valid values are:
1 'can_shortcut'
1 The register has a short cut in the pipeline;
1
1 'cannot_shortcut'
1 The register does not have a short cut in the pipeline.
1
1 For example:
1 .extCoreRegister mlo, 57, r , can_shortcut
1 defines a read only extension core register, 'mlo', which is
1 register 57, and can short cut the pipeline.
1
1 '.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS'
1 ARC allows the user to specify extension instructions. These
1 extension instructions are not macros; the assembler creates
1 encodings for use of these instructions according to the
1 specification by the user.
1
1 The first argument, NAME, gives the name of the instruction.
1
1 The second argument, OPCODE, is the opcode to be used (bits 31:27
1 in the encoding).
1
1 The third argument, SUBOPCODE, is the sub-opcode to be used, but
1 the correct value also depends on the fifth argument, SYNTAXCLASS
1
1 The fourth argument, SUFFIXCLASS, determines the kinds of suffixes
1 to be allowed. Valid values are:
1 'SUFFIX_NONE'
1 No suffixes are permitted;
1
1 'SUFFIX_COND'
1 Conditional suffixes are permitted;
1
1 'SUFFIX_FLAG'
1 Flag setting suffixes are permitted.
1
1 'SUFFIX_COND|SUFFIX_FLAG'
1 Both conditional and flag setting suffices are permitted.
1
1 The fifth and final argument, SYNTAXCLASS, determines the syntax
1 class for the instruction. It can have the following values:
1 'SYNTAX_2OP'
1 Two Operand Instruction;
1
1 'SYNTAX_3OP'
1 Three Operand Instruction.
1
1 'SYNTAX_1OP'
1 One Operand Instruction.
1
1 'SYNTAX_NOP'
1 No Operand Instruction.
1
1 The syntax class may be followed by '|' and one of the following
1 modifiers.
1
1 'OP1_MUST_BE_IMM'
1 Modifies syntax class 'SYNTAX_3OP', specifying that the first
1 operand of a three-operand instruction must be an immediate
1 (i.e., the result is discarded). This is usually used to set
1 the flags using specific instructions and not retain results.
1
1 'OP1_IMM_IMPLIED'
1 Modifies syntax class 'SYNTAX_20P', specifying that there is
1 an implied immediate destination operand which does not appear
1 in the syntax.
1
1 For example, if the source code contains an instruction like:
1 inst r1,r2
1 the first argument is an implied immediate (that is, the
1 result is discarded). This is the same as though the source
1 code were: inst 0,r1,r2.
1
1 For example, defining a 64-bit multiplier with immediate operands:
1 .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
1 SYNTAX_3OP|OP1_MUST_BE_IMM
1 which specifies an extension instruction named 'mp64' with 3
1 operands. It sets the flags and can be used with a condition code,
1 for which the first operand is an immediate, i.e. equivalent to
1 discarding the result of the operation.
1
1 A two operands instruction variant would be:
1 .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
1 SYNTAX_2OP|OP1_IMM_IMPLIED
1 which describes a two operand instruction with an implicit first
1 immediate operand. The result of this operation would be
1 discarded.
1
1 '.arc_attribute TAG, VALUE'
1 Set the ARC object attribute TAG to VALUE.
1
1 The TAG is either an attribute number, or one of the following:
1 'Tag_ARC_PCS_config', 'Tag_ARC_CPU_base', 'Tag_ARC_CPU_variation',
1 'Tag_ARC_CPU_name', 'Tag_ARC_ABI_rf16', 'Tag_ARC_ABI_osver',
1 'Tag_ARC_ABI_sda', 'Tag_ARC_ABI_pic', 'Tag_ARC_ABI_tls',
1 'Tag_ARC_ABI_enumsize', 'Tag_ARC_ABI_exceptions',
1 'Tag_ARC_ABI_double_size', 'Tag_ARC_ISA_config',
1 'Tag_ARC_ISA_apex', 'Tag_ARC_ISA_mpy_option'
1
1 The VALUE is either a 'number', '"string"', or 'number, "string"'
1 depending on the tag.
1